The Art of Assembly Language

Chapter 2: Numeric Representation

Figure 2-1: Tally-slash representation of 25

Figure 2-2: A positional numbering system

Figure 2-3: Bit numbering in a byte

Figure 2-4: Bit numbers in a word

Figure 2-5: The two bytes in a word

Figure 2-6: Bit layout in a double word

Figure 2-7: Bytes and words in a double word

Figure 2-8: BCD data representation in a byte

Chapter 3: Binary Arithmetic and Bit Operations

Figure 3-1: Decimal division (3456/12)

Figure 3-2: Longhand division in binary

Figure 3-3: Shift left operation (on a byte)

Figure 3-4: The shift right operation (on a byte)

Figure 3-5: Arithmetic shift right operation (on a byte)

Figure 3-6: Short packed date format (16 bits)

Figure 3-7: Long packed date format (32 bits)

Figure 3-8: Social Security number packed fields encoding

Figure 3-9: A (possibly) improved encoding of the Social Security number

Figure 3-10: Inserting ThirdField into the Social Security packed type

Chapter 4: Floating-Point Representation

Figure 4-1: Simple floating-point format

Figure 4-2: Single-precision (32-bit) floating-point format

Figure 4-3: Double-precision (64-bit) floating-point format

Figure 4-4: Extended-precision (80-bit) floating-point format

Chapter 5: Character Representation

Figure 5-1: ASCII codes for E and e

Figure 5-2: HLA string format

Figure 5-3: Overlapping strings using descriptors

Figure 5-4: Delphi/Kylix string data format

Figure 5-5: HLA character set representation

Chapter 6: Memory Organization and Access

Figure 6-1: Typical von Neumann machine

Figure 6-2: Memory write operation

Figure 6-3: Memory read operation

Figure 6-4: Byte, word, and double-word storage in memory (on an 80x86)

Figure 6-5: 8-bit CPU <-> memory interface

Figure 6-6: Byte addressing in word memory

Figure 6-7: 16-bit processor memory organization (e.g., 80286)

Figure 6-8: 32-bit processor memory interface

Figure 6-9: Accessing a word on a 32-bit processor at (address mod 4) = 3

Figure 6-10: Byte layout in a double word on the 80x86 processor

Figure 6-11: Alternate byte layout in a double word

Figure 6-12: Endian conversion in a double word

Figure 6-13: Layout of a union versus a record (struct) in memory

Figure 6-14: A C union on a little endian machine

Figure 6-15: A C union on a big endian machine

Figure 6-16: The system clock

Figure 6-17: A typical memory read cycle

Figure 6-18: A typical memory write cycle

Figure 6-19: Decoding and buffer delays

Figure 6-20: Inserting a wait state into a memory read operation

Figure 6-21: A two-level caching system

Chapter 7: Composite Data Types and Memory Objects

Figure 7-1: Memory allocation with malloc(sizeof(int) * 8)

Figure 7-2: Array layout in memory

Figure 7-3: Adding padding bytes before an array

Figure 7-4: Mapping a 4x4 array to sequential memory locations

Figure 7-5: Row-major array element ordering

Figure 7-6: Another view of row-major ordering for a 4—4 array

Figure 7-7: Column-major array element ordering

Figure 7-8: Student data structure storage in memory

Figure 7-9: Layout of a union versus a record variable

Chapter 8: Boolean Logic and Digital Design

Figure 8-1: Two-, three-, and four-variable truth maps

Figure 8-2: A truth map for F = C'B'A + C'BA' + C'BA + CB'A' + CB'A + CBA' + CBA

Figure 8-3: Surrounding rectangular groups of ones in a truth map

Figure 8-4: Truth map for F = C'B'A' + C'BA' + CB'A + CBA'

Figure 8-5: First attempt at surrounding rectangles formed by ones

Figure 8-6: Correct rectangle for the function

Figure 8-7: Truth map for F = C'B'A' + C'BA' + CB'A' + C'AB + CBA' + CBA

Figure 8-8: Obvious choices for rectangles

Figure 8-9: Correct set of rectangles for F = C'B'A' + C'BA' + CB'A' + C'AB+CBA'+CBA

Figure 8-10: Partial pattern list for a 4—4 truth map

Figure 8-11: Truth map for F = D'C'B'A' + D'C'B'A + D'C'BA + D'C'BA' + D'CB'A + D'CBA + DCB'A + DCBA + DC'B'A' + DC'BA'

Figure 8-12: Two combinations yielding three terms

Figure 8-13: AND, OR, and inverter (NOT) gates

Figure 8-14: The NAND gate

Figure 8-15: Inverter built from a NAND gate

Figure 8-16: Constructing an AND gate from two NAND gates

Figure 8-17: Constructing an OR gate from NAND gates

Figure 8-18: Building an n-bit adder using half and full adders

Figure 8-19: Seven-segment display

Figure 8-20: Seven-segment values for '0' through '9'

Figure 8-21: Adding four 256-MB memory modules to a system

Figure 8-22: Instruction (opcode) format for a very simple CPU

Figure 8-23: Encoding the MOV(EAX, EBX); instruction

Figure 8-24: Decoding simple machine instructions

Figure 8-25: Set/reset flip flop constructed from NAND gates

Figure 8-26: Implementing a D flip-flop with NAND gates

Figure 8-27: An 8-bit register implemented with eight D flip-flops

Figure 8-28: A 4-bit shift register built from D flip-flops

Figure 8-29: A 4-bit counter built from D flip-flops

Figure 8-30: A simple 16-state sequencer

Chapter 9: CPU Architecture

Figure 9-1: Patch board programming

Figure 9-2: Encoding instructions

Figure 9-3: Encoding instructions with source and destination fields

Figure 9-4: CPU design with a prefetch queue

Figure 9-5: A pipelined implementation of instruction execution

Figure 9-6: Instruction execution in a pipeline

Figure 9-7: A pipeline stall

Figure 9-8: A typical Harvard machine

Figure 9-9: Using separate code and data caches

Figure 9-10: A data hazard

Figure 9-11: How a CISC CPU handles a data hazard

Figure 9-12: A CPU that supports superscalar operation

Chapter 10: Instruction Set Architecture

Figure 10-1: Separating an opcode into several fields to ease decoding

Figure 10-2: Encoding instructions using a variable-length opcode

Figure 10-3: Basic Y86 instruction encoding

Figure 10-4: Single-operand instruction encodings (iii = %000)

Figure 10-5: Zero-operand instruction encodings (iii = %000 and rr = %00)

Figure 10-6: Jump instruction encodings

Figure 10-7: Encoding the add(cx, dx); instruction

Figure 10-8: Encoding the add(5, ax); instruction

Figure 10-9: Encoding the add([$2ff+bx], cx); instruction

Figure 10-10: Encoding the add ([1000], ax); instruction

Figure 10-11: Encoding the add ([bx], bx); instruction

Figure 10-12: Encoding the not(AX); instruction

Figure 10-13: Using a prefix byte to extend the instruction set

Figure 10-14: 80x86 instruction encoding

Figure 10-15: 80x86 add opcode

Figure 10-16: mod-reg-r/m byte

Figure 10-17: The sib (scaled index byte) layout

Figure 10-18: Encoding the add(al, cl); instruction

Figure 10-19: Encoding the add(eax, ecx); instruction

Figure 10-20: Encoding the add(disp, edx); instruction

Figure 10-21: Encoding the add([ebx], edi); instruction

Figure 10-22: Encoding the add([esi+disp _8] , eax); instruction

Figure 10-23: Encoding the add([ebp+disp ₃₂ ], ebx); instruction

Figure 10-24: Encoding the add([disp32+eax*1], ebp); instruction

Figure 10-25: Encoding the add([ebx+edi*4], ecx); instruction

Figure 10-26: Encoding an add immediate instruction

Chapter 11: Memory Architecture and Organization

Figure 11-1: The memory hierarchy

Figure 11-2: Possible organization of an 8-KB cache

Figure 11-3: Selecting a cache line in a direct-mapped cache

Figure 11-4: A two-way set associative cache

Figure 11-5: Translating a virtual address to a physical address

Figure 11-6: Typical Windows run-time memory organization

Figure 11-7: Heap management using a list of free memory blocks

Figure 11-8: Memory fragmentation

Figure 11-9: Freeing a memory block

Chapter 12: Input and Output (I/O)

Figure 12-1: A typical output port

Figure 12-2: An output port that supports read/write access

Figure 12-3: An input port and output device that share the same address (a dual I/O port)

Figure 12-4: Outputting data to a port by simply accessing that port

Figure 12-5: Outputting data using the read/write control as the data to output

Figure 12-6: Connection of the PCI and ISA buses in a typical PC

Figure 12-7: The AGP bus interface

Figure 12-8: Tracks and sectors on a hard disk platter

Figure 12-9: Multiple platter hard disk assembly

Figure 12-10: A hard disk cylinder

Figure 12-11: Interleaving sectors

Figure 12-12: Block list for small files

Figure 12-13: Block list for medium- sized files

Figure 12-14: Three-level block list for large files (up to 4 GB)