Pcb Applications

High Speed Digital Design Online Newsletter , Vol 3, Issue 12 Sal Aguinaga writes

I have 16 differential pairs that go through a connector and terminate on a daughter card. What is the best signal-to-ground ratio and pattern I should consider?

In this case the connector is a high-density pin connector. If the differential impedance is 100 W , do I need a special ground pattern as the signals go through the connector to maintain the differential impedance close to 100 W ?

Reply

Thanks for your interest in High-Speed Digital Design .

Regarding your correspondence, there is no general formula for the number of grounds required, as it depends on the spacing and sizes of the connector pins, and how they are bent.

Here are a few thoughts for you to consider.

• In a connector with an open field of pins, put the two elements of each differential pair on the same row of the connector. That will ensure that they get the same pin lengths and go through the same pattern of elbow bends. [52]
• On a synchronous bus, if you have enough time to wait for the crosstalk to settle , you may not need to isolate the differential pairs from each other.
• If isolation between pairs is required (for low crosstalk between nonsynchronized bus signals or for a clock or other asynchronous signal), place the pairs so that no signal wire from one pair falls adjacent to any wire from another pair. This implies that you will be using at least as many grounds as signal pins to separate the pairs, and probably more.

The differential impedance of most open-pin-field connectors is probably going to be a little higher than you want. You can measure this. You will need a pair of test boards on which you can mate the connector halves. The boards don't use any traces. They can be solid copper with holes drilled for the connector pins. Ground all the pins that will be grounded (or tied to a power plane) in your application. Use two RG-174 50- W coaxial cables to route a differential, 100- W signal into the designated signal pin pair. Let this signal go through the connector to the far side. On the far side of the connector, terminate the signal differentially with 100 W .

For any signal speed that will work with an open-pin-field connector, you will find that a 1/8-watt axial , 100- W resistor works fine as a terminator.

Blast in a differential signal from your 100- W source. Make a record of the resulting waveform as measured at the source. This should show the source waveform going out and a first reflection coming back (you've made a crude TDR instrument). Use a step risetime commensurate with what you are going to be using in the real system.

Don't mess around with fancy 35-ps step edges on this type of connector. They will just show you a bunch of fine-structure detail that isn't going to matter in the real system.

Now disconnect the coaxial cables from the connector. Place the 100- W termination directly across the coaxial cable outputs, with the coaxial grounds tied together. Repeat the measurement. You should ( ideally ) see no reflection.

Looking at the difference between the first measurement and the second, if the reflected waveform bumps up in the positive direction (same polarity as the step input), the connector impedance is a little too high. If it bumps negative, the connector impedance is too low. If you don't see a bump then the impedance is just right.

Adding more ground pins around the signal pair lowers the impedance.

Spacing the signal pins further away from ground raises the impedance.

Bonus idea: Adding a little lumped-element capacitance from signal to ground on each side will lower the effective impedance. This may be implemented in the pcb layout by just using larger-than-normal via pads. Experimentation and remeasurement is required to get this idea to work. The "big-pad" concept works when the connector through-delay is less than 1/6 of the signal risetime and the connector is acting like a lumped-element inductor (too high an impedance).

where

t UNCERTAINTY is the uncertainty (skew) in the clock switching moment,

V IH and V IL are the worst-case guaranteed high and low logic thresholds respectively, and

dv / dt is the rate of change of voltage on the clock input ( roughly equal to the logic swing D V divided by the 10% to 90% risetime of the driver). [53]

High Speed Digital Design Online Newsletter , Vol 1, Issue 10 Fabrizio Zanella writes to the SI List

I understand the benefits of using differential pairs for signals running at 100MHz and above. Can you speak about the impact of using differential clocks in a parallel bus? Do the differential clocks maintain the noise suppression characteristics when daisy-chained in a multidrop environment? Has anyone tried this and had positive experiences versus single-ended multidrop clocks?

Reply

Thanks for your interest in High-Speed Digital Design .

In general, I have found differential distribution to be a very effective means of combating ground bounce in the transmitting package, ground bounce in the receiving package, as well as the ground shifts that occur on either side of the connectors in high-speed systems. These benefits accrue in multidrop configurations as well as point-to-point configurations.

I have found differential distribution to be of little value in reducing the impact of crosstalk generated locally by other traces on the same pcb. This is because the crosstalk function from nearby traces falls off very steeply with distance. The impact of this is that differential pairs cannot be placed particularly close to any aggressive signal. For example, imagine a system that has one aggressive trace and a nearby victim trace that is receiving unacceptable amounts of crosstalk. Now I propose to protect the victim trace by splitting it into a differential pair and using a true differential receiver. Assuming that I don't want to affect the layout density, I plan to implement the centerline of the new pair right on top of the original victim trace. In other words, when we split the victim, one member of the pair will have to move closer to the offending source, while the other moves away. Unless the two traces of the pair are extremely close together (less than a third of the original separation between centerlines), the extra crosstalk we pick up from the nearby side of the differential pair overwhelms any "balancing" effect we might have hoped to gain from the far side of the differential system. To mitigate this effect, you have to separate the victim pair from the aggressive signal. In the final analysis, it's usually the extra separation that is providing most of the crosstalk benefit, not the fact of balanced signal distribution. When you want to battle crosstalk picked up on a pcb (over a solid ground plane), increasing the trace separation will probably result in a more dense design than using differential distribution.

For clocks, I see differential signaling used a lot, both in point-to-point distribution and in multidrop distribution. The multidrop aspect does not diminish the ground-bounce-canceling properties of differential signaling. There are only a few clock nets in a system (compared to the number of data nets ) and it isn't that difficult to provide this extra measure of protection.

For parallel bus signals, I rarely see differential distribution used because it doubles the number of wires required. That will cause the phenomenon known as "routing headaches " among your pcb layout staff.

Article first published in EDN Magazine , June 8, 2000

I am designing a piece of equipment to interface to a digital tape recorder designed by another company. This recorder uses a differential ECL interface, and the user 's manual recommends terminating the clock lines slightly differently from the data lines. Each clock line employs a split terminator (160- W to “5.2V and 100- W to ground), but the data signals simply use a single 120- W resistor between the wires of each pair. Because these two methods are Thevenin equivalents, why does the user's manual recommend different termination schemes? As far as I can tell, the transmitters and receivers for the clock and data lines are electrically equivalent, and all signals have 390- W pull-down resistors to “5.2V at the transmitter to properly bias their emitter-follower outputs. I have contacted the company that designed the circuit, but the original designers are unavailable. Does one termination scheme have any advantage over the other?

”Raymond Bullington

Engineers often have a difficult time figuring out why something was done. Sometimes there is no reason, sometimes there is a multitude of good reasons, and sometimes (as is common in the standards world) everyone wants it done the same way but all for conflicting and different reasons.

Anyway, differences do exist between the termination schemes you described. The single-resistor scheme (120 W across the two lines) terminates all differential-mode signals into 120 W but provides no termination for common-mode signals.

Your four-resistor scheme (independent terminations for each line) terminates all differential signals and all common-mode signals. The difference between these two styles matters only if a common-mode signal is present. And where might a common-mode signal come from? It can come from any skew naturally present in the clock driver output plus any imbalances in the circuit that convert part of the output from the differential mode to the common mode.

Every long, differential link needs a differential termination for signal quality and also a common-mode termination to prevent common-mode resonance .

Consider the single-resistor termination shown in Figure 6.26. Say that a positive-going edge x ( t ) arrives first on trace A, and then, after a tiny skew interval D t , the opposite signal “ x ( t “ D t ) arrives on trace B. During the tiny skew interval D t , the single 120- W resistor R1 creates two tiny artifacts. First, the initial rising edge on line A shoots right through the resistor onto trace B, creating a little blob of crosstalk. The amplitude of the crosstalk compared to the amplitude of the incoming signal is 1/2. Second, coincident with the crosstalk, you get a small signal reflected back onto line A. The amplitude of the reflected signal compared to the amplitude of the incoming signal is also 1/2. Both artifacts have positive polarity, creating what amounts to a common-mode reflection.

Figure 6.26. A network of two resistors terminates each half of the differential pair independently.

After time D t , the opposite signal “ x ( t “ D t ) arrives on line B. At this time you get a second set of crosstalk and reflection artifacts, but with negative polarities this time (because they originated on the negative half of the differential pair). The second set of artifacts partially cancels the first, with the degree of cancellation depending on the exact temporal alignment of the two signals. The two sets of artifacts perfectly cancel only when the signals on A and B arrive in perfect synchronism.

In this example, both the crosstalk and reflection amplitude coefficients equal 1/2. You may express the residual common-mode signal g ( t ), induced on either trace by the single-resistor end-terminator, as g ( t ) = (1/2)( x ( t ) “ x ( t “ D t )). If the skew is less than the signal rise or fall time t 10 “90 , and you define the signal step height as D V , the peak amplitude of the reflected common-mode noise roughly equals (1/2) D V ( D t / t 10 “90 ).

Once created, the common-mode noise returns to the driver. In your case, the ECL driver presents a very low output impedance to the line, generating a big reflection. The reflected noise then proceeds to the receiver, where it once again encounters the single-resistor termination, but this time as a purely common-mode signal. Because a common-mode signal presents the same voltage on both traces, the single-resistor terminator draws zero current and acts as an open circuit. The open circuit generates another big reflection. After that point, the common-mode noise trapped on the line happily bounces back and forth between the driver (low impedance) and the receiver (open circuit) for a long time.

Terrible things happen to the common-mode noise if your trace delay equals one-quarter of the clock period. In that case, the little common-mode artifacts from each edge build and superimpose, cycle after cycle, magnifying the common-mode noise at the receiver and also magnifying the common-mode radiated emissions. This problem is called a common-mode resonance .

To avoid common-mode resonance, every long, differential link needs two terminations: first, a good differential termination at one end or the other to provide good differential signal quality, and second, a reasonable common-mode termination at one end or the other to prevent severe common-mode resonance. An ECL driver does not provide a good common-mode termination at the source; therefore, one is required at the load.

The four-resistor termination that was recommended to you for the end of the clock net independently terminates both lines, damping both differential and common-mode signals at that point.

An even better termination circuit appears in Figure 6.26. This circuit terminates both differential and common-mode signals but requires only two resistors (R2 and R3 are each set to half the differential-line impedance). The capacitor need be only large enough to hold its charge steady during the brief interval of skew D t . In your case the ECL sources incorporate pull-down resistors, so you don't need to supply a special terminating voltage ( V T ) to the capacitor.

Any driver that provides a reasonable common-mode termination at the source relieves you of the responsibility of providing one at the destination. For example, a source- terminated driver works fine with the single-resistor termination.

Article first published in EDN Magazine , September 1, 2000

What is the effect of a split in a solid plane on the impedance of a coplanar differential pair? The differential pair passes over a solid plane (logic return) and then crosses a 50-mil void into an I/O area that has a solid plane of its own that is tied to the chassis .

”Boris Shusterman

Significant currents flow on the solid reference plane beneath your differential traces. Cutting the plane interrupts these currents.

Consider first a single-ended pcb trace. When a changing voltage propagates down a single-ended transmission structure, currents flow through the distributed capacitance of the trace to all nearby objects, especially the big, solid plane underneath the trace. This capacitive effect generates a returning (reverse) flow of current on the solid reference plane. The return current flows all the way back to the source along the reference plane, staying underneath the signal trace the whole way, making a complete circuit. (Current always makes a loop.)

Counteract the U-turn by shrinking both the reference-plane gap and the spacing between traces .

Now, consider a differential-pcb-trace pair. Differential structures have capacitance from each trace individually to the reference plane and also between the traces. The between-trace, or mutual, capacitance of the differential pair induces returning current on the other trace as well as on the solid reference plane. In a differential-pcb pair, most of the returning current from each trace still flows on the solid plane, not the other trace, because each differential trace couples much more strongly to the big, solid nearby plane than it does to its little, skinny differential buddy.

Try to visualize the propagation of a differential signal as a quad of four currents: two currents, i+ and i “, on the two signal traces, and the returning currents, r+ and r “, on the reference plane underneath the traces (Figure 6.27). In most cases the currents are almost as big as i+ and i “.

Figure 6.27. The U-turn zone at a reference-plane gap separates the return currents from the primary signal currents on traces A and B.

When a differential signal encounters the gap between reference planes, the two signal currents continue across the gap on the signal wires, but the gap blocks the two return currents r+ and r “. This situation forces the return currents to execute a U-turn maneuver, whereby each return current U-turns into the other position. On the new reference plane, a similar effect takes place with a second U-turn formation creating a pair of currents r'+ and r' “ to complete the quad current formation.

In the space between the reference planes, current circulates clockwise on all sides of the U-turn zone. This current behaves like a small current-loop antenna, generating a substantial, fast-changing magnetic field within the U-turn zone.

The magnetic field makes the circuit behave as if an inductor were in series with the signal path. The length and width of the U-turn zone determine the inductance. For example, a trace-to-trace separation of 0.100 in. and a plane-to-plane separation of 0.100 in. would generate an inductance on the order of 10 nH, which in a 100- W differential system would introduce a low-pass filter response with a time constant of 100 psec. If risetime exceeds 1 nsec, you probably won't even notice the effect. On the other hand, at very high speeds, a 100-psec risetime could mess up your signals.

The U-turn zone is more than merely a region of increased impedance due to the absence of the reference planes. It is an effect whose physical dimensions span both the gap between planes and the spacing between traces. You counteract the U-turn by shrinking both the reference-plane gap and also the spacing between traces. You can also practically eliminate it by providing continuous pathways adjacent to each signal trace for the conveyance of return currents from plane to plane, eliminating the need for a U-turn zone. If the planes carry different DC voltages, a bypass capacitor next to each trace isn't perfect, but it helps.

The magnetic fields within the U-turn zone induce crosstalk and EMI. The crosstalk couples to all the differential pairs that pass over the same gap. Both EMI and crosstalk vary in proportion to the size of the U-turn zone.

Article first published in EDN Magazine , April 18, 2002

Passing through a sharp turn with an edge-coupled differential pair, the outside trace travels further than the inside trace. The difference in distance traveled contributes a small amount of skew to your differential signals. The skew acts as a mode converter, changing part of your differential signal power into common-mode power.

The pair-turning skew becomes noticeable only when the skew contributed by the turn rises to a level comparable with the natural skew already coming out of your driver. Therefore, before worrying about turns, first determine the skew of your driver. In many cases the driver skew is not specified, in which case you can assume the skew will be at least 10% of the signal risetime. Digital differential drivers just aren't balanced very well. Analog transceivers often are, which accounts for the importance of meticulous skew-matching in some analog applications.

Chamfering or rounding of differential corners does not eliminate skew .

For example, let's say an Ethernet 100BASE-TX LAN transceiver with a well-balanced output transformer and common-mode choke puts out differential signals balanced to 1 part in 1000 ”meaning that the common-mode output is 1000 times smaller than the differential signal. To avoid amplifying the common-mode signal on the wires (and thereby the radiation), the aggregate skew contributed by all components used with this transceiver must remain less than 1/1000 of 1 risetime. The risetime of a 100BASE-TX signal is approximately 8 nS, corresponding to roughly 94 inches of propagation in air, 1/1000 of which works out to 0.094 in., so the skew budget within cable connectors and board layout should be set somewhere around 0.1 inch. Worrying about little bitty skew effects much smaller than 0.1 inch doesn't buy you anything.

To take a faster example, a 2.5 Gb/s serial link driver with a risetime of 200 ps has an output skew of probably no better than 20 ps (maybe a lot worse ). In this case a skew budget of perhaps 20 ps seems reasonable.

Figure 6.28 illustrates the skew calculations for three alternative corner treatments , each with a trace pitch (centerline to centerline) of p . In each case, the two traces within the pair share the same number and type of sharp corners (diagonal-striped regions ). The differences between the inside and outside traces are shaded dark with white lettering. The lengths added to the outside trace are 2 p , 1.65 p , and 1.57 p respectively for the three corner styles. Apparently, chamfering or rounding of differential corners does not eliminate skew; it only makes at best a modest improvement.

Figure 6.28. These three corner treatments all generate similar amounts of skew.

If your trace separation p equals 20 mils, and the propagation delay of your media is 160 ps/in., the skew associated with a distance of p is (0.020 in. x 160 ps/in.) = 3.2 ps. According to Figure 6.28, the skew accumulated when rounding a corner of any of the three types shown ranges in that case from a high of 2 p 6.4 ps to a low of 1.57 p 5.0 ps. If this amount of skew is superceded by the skew from your driver, then don't worry about the turns.

When skew becomes a problem, you can mitigate its impact in two ways. First, use a smaller spacing. The smaller you make p , the less skew you will get. This is one of the few benefits of tightly coupled pairs. Second, position your ICs so the traces leave the driver headed in the same direction that they enter the receiver. For example, a differential pair that starts out headed north and ends up headed north has by definition equal numbers of right- and left-hand turns no matter what happens in the middle (unless it makes a spiral), so the net skew accumulated is zero.

Article first published in EDN Magazine , May 2, 2002

The previous article "Your Layout Is Skewed" concerned various styles of corners and bends normally used on differential edge-coupled pairs. It pointed out that all corners, whether chamfered or not, add extra length to the outside trace as it rounds the bend. The equivalent trace length added by 90 worth of bending ranges from one and one half to two times the intrapair trace pitch depending on how the corner is chamfered. The extra time added to the outside trace is a form of intrapair skew.

This article considers two strategies for minimizing the intrapair skew accumulated by a differential net. The six BGA chips within the dotted -line region in Figure 6.29 illustrate the first strategy.

Figure 6.29. The positioning of entrances and exits affects the intra-pair skew.

Pair A exits the bottom chip heading north. It enters the receiver (top chip) also heading north. Along the way, this pair takes one right turn and one left turn. The skew accumulated in the two successive turns cancels to zero .

In a general routing problem, the number and types of turns required depends on the relative orientations of the driver and receiver. Because pair A starts and ends going in the same direction, this pair will always make equal numbers of right-hand and left-hand turns no matter what happens in the middle (unless it makes a spiral). The net skew accumulated on any pair with a chip floor plan like A is zero.

Pair B doesn't fare as well. It exits the bottom chip headed east. It takes one left turn to get going north (the orientation of the receiver), after which the number of left and right turns remain balanced. The total skew accumulated by pair B equals the amount generated by one left-hand turn.

Pair C is the worst of all. It exits to the east and enters to the west. It therefore requires two extra left turns to achieve the correct orientation. If you are going fast enough so that every turn worth of skew matters, you should carefully plan your chip orientations so the accumulated skew naturally balances to zero.

A pair that starts and ends going north has by definition equal numbers of right-hand and left-hand turns .

The second strategy concerns the precise manner in which your pair enters or exits a ball grid array (or any field of connector pins, package pins, or vias). This strategy works best when the ball pitch exceeds the intrapair trace pitch. It works by offsetting the centerline of the pair as it enters (or exits) the BGA, as shown in the figure at D . By offsetting the top pair down half a position, extra time delay accrues to the topmost trace. Offsetting the bottom pair up half a position adds time to the bottommost trace. This strategy "buys some time," which you can use to pay for other floor planning inadequacies. It isn't perfect, but it delivers what you need ”balanced skew.

When you have to adjust the skew, I favor doing it near either the driver or the receiver, whichever has the poorest termination. That way the skew adjustment can't possibly affect the quality of the good termination at the other end of the line. If both ends have high-quality terminations, then you place the adjustment at either end. In an imperfect world, that's as well as you can do.

To those who yearn for a perfect layout with zero bends I say, with all due credit to the Rolling Stones, "You can't always get what you waaaannnnnnnt... You can't always get what you waaaannnnnnnt... but if you buy some time, you just might find, you'll get what you need."

Oooh, yeah!