HP-UX CSE(c) Official Study Guide and Desk Reference

Number of logic gates = 200 + 30 = 230

First instruction appears after 230 units of time

Second instruction starts after 150 logic gates, i.e., the "glue" kicks in. Therefore, the second and subsequent instructions appear after 30+150=180 units of time.

We have 100 instructions in our instruction stream. Time to execute = 230 + 99 * 180 = 18050

Time to execute non-pipelined instruction stream = 200 * 100 = 20000

1 pipeline = 150 gates = 150 units of time

Having separate caches for instructions and data allows parallel access to instructions and data and hence improves the effectiveness of pipelining. Having a unified cache will slow the pipeline down due to contention when accessing either instructions or data: That's a demonstration of the von Neumann bottleneck.

You want a "long" cache line because multiple data elements can be stored in a single cache line and, hence, accessed quicker. Applications with more "random" data access patterns would benefit from "shorter" cache lines because subsequent accesses will probably require a new cache line to be fetched . With "shorter" cache lines, we can have more cache lines for the same size cache.

Answer: A Direct Mapped cache.

Answer: 16.

Take the 2-bit sequence 10 as our encoded cache "set number." This needs to map to four separate locations. Using the binary line number, we can see why having 16 lines works: The shaded boxes are for our four-way set.