Real Time UML: Advances in the UML for Real-Time Systems (3rd Edition)

Figure 1-1: Synchronization Patterns

Figure 1-2: «active» Objects and Threads

Figure 1-3: Required and Offered Quality of Service

Figure 1-4: Priority Inversion Model

Figure 1-5: Priority Inversion Scenario

Figure 1-6: ROPES Spiral Macrocycle

Figure 1-7: ROPES SemiSpiral Lifecycle

Figure 1-8: ROPES Spiral

Figure 1-9: ROPES Process Artifacts

Figure 1-10: MDA Overview

Figure 1-11: The MDA Approach

Figure 1-12: Sample Schedule

Figure 1-13: Resource Histogram

Figure 1-14: Use Case-Based Model of Organization

Figure 1-15: Framework-Based Model Organization

Figure 1-16: Logical Model-Based Model Organization

Figure 1-17: Physical Model-Based Model Organization

Figure 1-18: Model Execution

Figure 2-1: Object Abstraction

Figure 2-2: Objects and Classes

Figure 2-3: Objects and Classes in Use

Figure 2-4: Interfaces

Figure 2-5: Sending Messages

Figure 2-6: Simple Association

Figure 2-7: Association, Aggregation, and Composition

Figure 2-8: Composition and Parts

Figure 2-9: Generalization

Figure 2-10: Dependency

Figure 2-11: Packages

Figure 2-12: Structured Classes

Figure 2-13: Interfaces, Connections, and Ports

Figure 2-14: Components

Figure 2-15: Subsystems

Figure 2-16: Subsystem Example

Figure 2-17: Nodes and Deployment

Figure 2-18: Levels of Abstraction in Architecture

Figure 2-19: Subset of UML Metamodel for Structural Elements

Figure 2-20: Constraints in Action

Figure 3-1: State Machine for an Object

Figure 3-2: Telephone Statechart

Figure 3-3: State Internal Features

Figure 3-4: Statechart of Object with And-States

Figure 3-5: UML Pseudostates

Figure 3-6: Branches and Junctions

Figure 3-7: History

Figure 3-8: Forks and Joins

Figure 3-9: Referencing State Machine; OnHook and OffHook Submachines

Figure 3-10: Inherited Statecharts

Figure 3-11: Ill-Formed Statechart

Figure 3-12: Pacemaker Class Diagram

Figure 3-13: Communications Subsystem

Figure 3-14: Pacing Engine Subsystem

Figure 3-15: ReedSwitch State Model

Figure 3-16: CoilDriver State Model

Figure 3-17: Communications Manager State Model

Figure 3-18: Processing Statechart

Figure 3-19: Chamber Model State Model

Figure 3-20: Atrial Model State Model

Figure 3-21: Ventricular Model State Model

Figure 3-22: Protocol State Machine Context and Machines

Figure 3-23: Activity Chart

Figure 3-24: Additional Activity Diagram Notations

Figure 3-25: Sequence Diagram

Figure 3-26: Additional Sequence Diagram Annotations

Figure 3-27: Partial Ordering

Figure 3-28: Loops and Branches

Figure 3-29: Parallel Regions

Figure 3-30: Assert, Consider, Ignore?

Figure 3-31: Referencing Sequence Diagram

Figure 3-32: Lifeline Decomposition

Figure 3-33: Referenced Interaction Fragment

Figure 3-34: Simple State Timing Diagram

Figure 3-35: Timing Diagram with Multiple Lifelines

Figure 3-36: Simple Task Timing Diagram

Figure 3-37: Task Timing Diagram with Shading

Figure 3-38: Timing Diagram with Continuous Values

Figure 4-1: UML Stereotypes

Figure 4-2: Tagged Values and Constraints

Figure 4-3: Representing Tagged Values

Figure 4-4: RT UML Profile Use Cases

Figure 4-5: Usage Paradigm for the RT Profile

Figure 4-6: RT UML Profile Organization

Figure 4-7: Client-Server Basis of the GRM

Figure 4-8: Core Resource Model

Figure 4-9: Static Resource Usage Model

Figure 4-10: Causality Loop

Figure 4-11: Dynamic Resource Usage Model

Figure 4-12: Timing Marks

Figure 4-13: Concurrency Subprofile Domain Model

Figure 4-14: Concurrency Subprofile Stereotypes Example

Figure 4-15: Schedulability Domain Model

Figure 4-16: Schedulability Subprofile Example (Global RMA)

Figure 4-17: Schedulability Subprofile Example (Scenario Analysis)

Figure 4-18: Performance Domain Model

Figure 4-19: Performance Model Example (Structure)

Figure 4-20: Performance Model Example (Deployment)

Figure 4-21: Performance Model Example (Scenario)

Figure 4-22: Broker Pattern

Figure 4-23 Real-Time CORBA Domain Model

Figure 5-1: Requirements Taxomomy

Figure 5-2: Use Case Diagram

Figure 5-3: Air Traffic Control System Use Cases

Figure 5-4: Anesthesia Machine Use Cases

Figure 5-5: Anesthesia Subsystems

Figure 5-6: Decomposition of Deliver Anesthesia Use Case

Figure 5-7: Use Case Activity Breakdown

Figure 5-8: Ventilator Use Cases

Figure 5-9: User Interface Use Cases

Figure 5-10: Vaporizer Use Cases

Figure 5-11: SPO2 Monitor Use Cases

Figure 5-12: CO2 Monitor Use Cases

Figure 5-13: Agent Monitor Use Cases

Figure 5-14: Breathing Circuit Use Cases

Figure 5-15: Bad Use Case Modeling

Figure 5-16: Textual Characterization of Use Cases

Figure 5-17: Use Case Relations

Figure 5-18: ECG Use Cases

Figure 5-19: Use Cases in Development

Figure 5-20: Relating Text and Scenarios

Figure 5-21: Use Case Sequence Diagram

Figure 5-22: Deliver Anesthesia Collaboration

Figure 5-23: Elaborated Scenario Part 1

Figure 5-24: Elaborated Scenario Part 2

Figure 5-25: Alarm On Critical Event Requirements

Figure 5-26: Alarm On Critical Event Statechart

Figure 5-27: Statecharts and Text

Figure 5-28: Statecharts and Sequence Diagrams

Figure 5-29: Display Waveform Activity Diagram

Figure 5-30: Use Case Timing Diagram

Figure 6-1: ROPES Nanocycle for Domain Analysis

Figure 6-2: Use Cases, Collaborations, and Objects

Figure 6-3: Domains

Figure 6-4: Information Flows

Figure 6-5: Elevator Central Station Main View

Figure 6-6: Elevator Central Station Menu View

Figure 6-7: Elevator Central Station Zoom View

Figure 6-8: Pace the Heart in AAI Mode (Use Case Level)

Figure 6-9: Pacemaker Object Collaboration

Figure 6-10: Pace the Heart in AAI Mode (Object Level)

Figure 6-11: First-Cut Elevator Object Diagram

Figure 6-12: Modeling Nonprimitive Attributes

Figure 6-13: Session Associative Class

Figure 6-14: Button Subclasses

Figure 6-15: Generalization and Constraints

Figure 6-16: Extending and Specializing

Figure 6-17: Positioning Attributes in the Generalization Hierarchy

Figure 6-18: Repositioned Attributes

Figure 7-1: Token-Flow Semantics

Figure 7-2: Retriggerable One-Shot Timer FSM

Figure 7-3: Message Transaction Structure

Figure 7-4: Message Transaction Behavior

Figure 7-5: Pacemaker Use Cases

Figure 7-6: Pacemaker Class Diagram

Figure 7-7: ReedSwitch State Model

Figure 7-8: CoilDriver State Model

Figure 7-9: Communications Gnome State Model

Figure 7-10: Chamber Model State Model

Figure 7-11: Chamber Model SelfInhibited Statechart

Figure 7-12: Chamber Model SelfTriggered Statechart

Figure 7-13: AtrialModel Dual Mode Statechart

Figure 7-14: VentricularModel Dual Mode Statechart

Figure 7-15: Calculator Use Cases

Figure 7-16: Calculator Classes

Figure 7-17: CharParser Statechart

Figure 7-18: Tokenizer Statechart

Figure 7-19: Evaluator Statechart

Figure 7-20: Stimulator Statechart

Figure 7-21: Event Hieracrchy/Reception

Figure 7-22: HeartChamber Actor Statechart

Figure 7-23: Inserting Events

Figure 7-24: Debugging with a Web Browser

Figure 7-25: Debugging View

Figure 7-26: CardioNada Sequence 1 Creation and Initialization

Figure 7-27: CardioNada Sequence 2 Pacing

Figure 7-28: CardioNada Sequence 3 Inhibiting

Figure 7-29: Debug Configuration

Figure 7-30: Calculator Scenario 2* (3+4) page 1

Figure 7-31: Calculator Scenario 2* (3+4) page 2

Figure 7-32: Calculator Scenario 2* (3+4) page 3

Figure 7-33: Calculator Scenario 2* (3+4) page 4

Figure 7-34: Calculator Scenario 2* (3+4) page 5

Figure 8-1: Three Levels of Design

Figure 8-2: Logical and Physical Architecture

Figure 8-3: Logical Domain Architecture

Figure 8-4: Relating Logical and Physical Architecture

Figure 8-5: Levels of Architectural Abstraction

Figure 8-6: The Five Views of Architecture

Figure 8-7: System View

Figure 8-8: Subsystem View

Figure 8-9: Component View

Figure 8-10: Concurrency and Resource View

Figure 8-11: Distribution View

Figure 8-12: Safety and Reliability View

Figure 8-13: Deployment View

Figure 8-14: Elevator Architecture

Figure 8-15: OSI Model Layered Architecture

Figure 8-16: Vertical Slices

Figure 8-17: Deployment Diagram Notation

Figure 8-18: Telescope Position Controller Deployment Diagram

Figure 8-19: Elevator Task Diagram

Figure 8-20: Concurrency in Active Objects

Figure 9-1: Observer Pattern

Figure 9-2: Observer Pattern Example Structure/Scenario

Figure 9-3: Proxy Pattern

Figure 9-4: Proxy Example Structure

Figure 9-5: Proxy Example Scenario

Figure 9-6: Transaction Pattern

Figure 9-7: Sender/Receiver Transaction Statechart

Figure 9-8: Reliable Transaction Example Structure/Scenario

Figure 9-9: Basic Smart Pointer Pattern/Wrapper Variant

Figure 9-10: Smart Pointer Cycles

Figure 9-11: Smart Pointer Pattern Structure/Scenario

Figure 9-12: Guarded Call Pattern Structure

Figure 9-13: Guarded Call Pattern Structure/Scenario

Figure 9-14: Container Pattern

Figure 9-15: Container Pattern Example

Figure 9-16: Rendezvous Pattern Structure

Figure 9-17: Thread Barrier Synch Policy Statechart

Figure 9-18: Rendezvous Pattern Scenario Example

Figure 10-1 Role Constraints and Qualified Associations

Figure 10-2: Detailed Design of Multivalued Roles

Figure 10-3: Balanced In-Order Tree

Figure 10-4: Unbalanced Tree after Adding Node 9

Figure 10-5: Rebalanced Tree

Figure 10-6: Left Rotation

Figure 10-7: Activity Diagram for Add Node Operation

Figure 11-1: Report on Model for AV-1 Overview

Figure 11-2: AV-2 Integrated Dictionary

Figure 11-3: OV-1 Operation Concept Diagram with Standard Notation

Figure 11-4: OV-1 Operational Concept Diagram in Rhapsody with Icons

Figure 11-5: OV-2 Operational Node Connectivity with Classes

Figure 11-6: OV-2 Operational Node Connectivity with Deployment Diagram

Figure 11-7: OV-3 Data Information Exchange

Figure 11-8: SV-1 System Interface Description

Figure 11-9: SV-1 Intrasystem Perspective

Figure 11-10: OV-4 Command Relationship Chart

Figure 11-11: OV-5 Operational Activity Model

Figure 11-12: OV-5 Operational Activity Mode with Swim Lanes

Figure 11-13: OV-5 Operational Activity Model with Two Agencies

Figure 11-14: OV-6a Logical Data Model for Operational Rules

Figure 11-15: OV-6b Statechart for Operation State Transition Description

Figure 11-16: OV-6c Event-Trace Description with Sequence Diagram

Figure 11-17: OV-7 Logical Data Model

Figure 11-18: SV-3 Systems-Systems Matrix with Class Diagram

Figure 11-19: SV-4 Systems Functionality Description

Figure 11-20: SV-6 Data Flow on Class Diagram

Figure 11-21: SV-7 Systems Performance on Class Diagram

Figure 11-22: SV-7 Systems Performance in Reports and Browser

Figure 11-23: SV-8 Systems Evolution Description

Figure 11-24: SV-11 Physical Schema with Deployment

Figure 11-25: SV-11 Physical Schema with Components

Additional figures appear in the Appendix.