ItaniumR Architecture for Programmers. Understanding 64-Bit Processors and EPIC Principles

Table 1-1 Generations of Computer Languages

Table 1-2 Prefixes for Binary Multiples

Table 1-3 Comparisons Among Computer Architectures by Intel Corporation

Table 1-4 Comparisons Among Computer Architectures by Digital Equipment Corporation

Table 1-5 Comparisons Among Computer Architectures by Hewlett-Packard and Intel

Table 1-6 Conversion Table for the First Few Integers

Table 1-7 Representations for Small Integer Values

Table 2-1 Integer Data Types

Table 2-2 IEEE Floating-Point Numbers

Table 2-3 ASCII Character Encoding

Table 3-1 Classes of Operators in SQUARES

Table 3-2 Specifying the Radix of Constants with Itanium Assemblers

Table 3-3 Assembler Directives for Storage Allocation

Table 3-4 Assembler Arithmetic and Logical Binary Operators

Table 3-5 Assembler Arithmetic and Logical Unary Operators

Table 3-6 Selected Debugger Commands for Itanium Programming Environments

Table 4-1 Itanium Instruction Types and Execution Unit Types

Table 4-2 Bit Encodings for Itanium Addition and Subtraction Instructions

Table 4-3 Characteristics of Itanium 2 Memory Hierarchy

Table 4-4 Effective Addresses for Itanium Addressing Modes

Table 4-5 Addressing Modes for Various Architectures

Table 5-1 Simplified Summary of Instruction Latency

Table 6-1 Boolean Functions of Two Variables

Table 6-2 Effect of Parallel Comparison Types

Table 6-3 Addition of Two Single-Bit Integers

Table 6-4 Operation at Step i in the Booth Algorithm

Table 7-1 High-Level Language Syntax for Passing Arguments

Table 7-2 Some Itanium Assembler Directives Related to Stack Unwinding

Table 8-1 Comparisons of Itanium Integer and Floating-Point Instructions

Table 8-2 Meanings of Special IEEE Floating-Point Representations

Table 8-3 Mnemonic Specifiers for Floating-Point Classes

Table 9-1 Calling Conventions for C Functions Related to stdin and stdout

Table 9-2 Calling Conventions for C Functions Related to Text Files

Table 10-1 Itanium 2 Processor General Pipeline

Table 10-2 Itanium Instruction Templates

Table 10-3 Assembler-Selected Templates for a Program Segment

Table 11-1 Command-Line Options for Optimization for gcc and g77 (Linux)

Table 11-2 Command-Line Options for Optimization for ecc and efc (Linux)

Table 11-3 Command-Line Options for Optimization for aCC, cc, and f90 (HP-UX)

Table 11-4 Compiler Output for the COM_C Program from gcc and ecc (Linux)

Table 11-5 Compiler Output for the COM_C and COM_F Programs (Linux)

Table 11-6 Compiler Output from cc_bundled and f90 (HP-UX)

Table 11-7 Two Levels of Optimization for COM_F Program (Linux)

Table 11-8 Loop Length Differences Using the f90 Compiler (HP-UX) at Level +O2

Table 11-9 Effect of Moving a Function Inline Using the cc Compiler (HP-UX)

Table 12-1 Flynn's Qualitative Classification of Computing Systems

Table 12-2 Itanium Integer Parallel Instructions

Table 12-3 Itanium Floating-Point Parallel Instructions

Table 13-1 Selected Characteristics of the First Two Itanium Processors

Table 13-2 Characteristics of the Cache Hierarchy for the Original Itanium Processor

Table 13-3 Possible Dual Issue of Bundles for Original and Itanium 2 (I2) Processors

Table 13-4 Original Itanium Processor General Pipeline

Table 13-5 Producer Consumer Latencies for the (Itanium) and Itanium 2 Processors

Table A-1 Line Terminators in Text Files

Table A-2 Comparison of DOS and HP-UX or Linux Commands

Table C-1 Instructions Listed by Function

Table C-2 Instructions Listed by Assembler Opcode

Table D-1 Itanium General Registers

Table D-2 Itanium Branch Registers

Table D-3 Itanium Predicate Registers

Table D-4 Itanium Floating-Point Registers

Table D-5 Itanium Application Registers

Table D-6 Definitions of Processor Status Bits

Table E-1 Itanium Assembler Mode Control Directives