Computer Systems Performance Evaluation and Prediction

Chapter 1: Introduction

Figure 1.1: Basic computer system.

Figure 1.2: Low-level memory access.

Figure 1.3: Typical CPU architecture.

Figure 1.4: Instruction cycle execution.

Figure 1.5: CPU memory access.

Figure 1.6: Memory hierarchy.

Figure 1.7: Basic computer architecture.

Figure 1.8: Alternative computer architecture.

Figure 1.9: Common bus architecture.

Figure 1.10: Dual bus architecture.

Figure 1.11: Modeling process.

Figure 1.12: Abstraction of a system.

Figure 1.13: Single server queue.

Chapter 2: Computer Data Processing Hardware Architecture

Figure 2.1: Basic processing unit of a computer.

Figure 2.2: CPU memory access.

Figure 2.3: The CPU and its associated registers.

Figure 2.4: Instrumentation execution cycle.

Figure 2.5: Memory access mechanism.

Figure 2.6: Memory hierarchy.

Figure 2.7: Schematic diagram of a magnetic tape storage system.

Figure 2.8: Schematic diagram of a magnetic or optical disk system.

Figure 2.9a: Multiprocessor computer system with distributed memory.

Figure 2.9b: Multiprocessor computer system with Simms memory.

Figure 2.9c: Multiprocessor computer system with private local memory.

Figure 2.9d: Multiprocessor computer system with a communications subsystem.

Figure 2.10: Connecting networks through a bridge.

Figure 2.11: Ring topology.

Figure 2.12: Basic computer architecture.

Figure 2.13: Computer architecture utilizing an I/O controller.

Figure 2.14: A computer system organized around memory.

Figure 2.15: Unibus architecture.

Figure 2.16: Dual bus architecture.

Figure 2.17: Computational engine.

Figure 2.18: Memory hierarchy.

Figure 2.19: Process states.

Figure 2.20: Process flow in a round-robin scheduler.

Figure 2.21: Multilevel time-slice scheduling.

Figure 2.22: A deadlock.

Figure 2.23: Memory map.

Figure 2.24: Fragmented memory.

Figure 2.25: Marking free blocks in memory.

Figure 2.26: Memory after garbage collection.

Figure 2.27: Memory with both paging and segmentation.

Figure 2.28: Spatial data management system.

Figure 2.29: Sample form.

Figure 2.30: Architecture to support a database system.

Figure 2.31a: Database transaction.

Figure 2.31b: ACID transaction.

Chapter 3: Fundamental Concepts and Performance Measures

Figure 3.1: Example of a computer clock.

Figure 3.2: Event partial orderings.

Figure 3.3: Example of intervals

Figure 3.4: Response time versus system load.

Figure 3.5: Cartesian product of two independent sample spaces.

Figure 3.6: System definition.

Chapter 4: General Measurement Principles

Figure 4.1: Probability distribution for a fair die.

Figure 4.2: Probability density function.

Figure 4.3: Probability distribution function.

Figure 4.4: Resource in equilibrium.

Chapter 5: Probability

Figure 5.1: Conditional probability space Venn diagram.

Figure 5.2: Outcomes of the message length experiment.

Figure 5.3: Example distribution functions.

Figure 5.4: Uniform density function.

Figure 5.5: A few normal curves.

Figure 5.6: Selected area under a normal distribution curve.

Figure 5.7: Exponential probability density function.

Figure 5.8: Exponential probability distribution function.

Figure 5.9: Erlang density functions for selected values of k.

Chapter 6: Stochastic Processes

Figure 6.1: Stochastic process for P[x≤t+h|x>t].

Figure 6.2: Independent stochastic processes.

Figure 6.3: Stationary stochastic processes.

Figure 6.4: Example phone call volume.

Figure 6.5: Two Poisson arrival streams merging.

Figure 6.6: Poisson stream dividing.

Figure 6.7: Possibility of a terminal failure.

Figure 6.8: Example birth-death process.

Figure 6.9: Example stochastic process state transition diagram.

Figure 6.10: Graphical representation for the birth-death process.

Figure 6.11: Transition rate diagram.

Figure 6.12: Mapping of Markov process to other stochastic processes.

Figure 6.13: Example probability state transition matrix.

Figure 6.14: State transition diagram.

Figure 6.15: Transition probability matrix.

Figure 6.16: Communications systems stages.

Figure 6.17: Transition probabilities for the communications systems of Figure 6.16.

Figure 6.18: Transition state diagram (Bernoulli trials, coin toss).

Figure 6.19: Reducible transition diagram.

Figure 6.20: State diagram.

Chapter 7: Queuing Theory

Figure 7.1: Single server model.

Figure 7.2: Queuing network model.

Figure 7.3: Stochastic processes and random variable notation.

Figure 7.4: Kendall notation.

Figure 7.5: Kendall notation symbol definitions.

Figure 7.6: M/M/1 queuing system model.

Figure 7.7: Exponential service distribution.

Figure 7.8: M/M/1 system state transition diagram.

Figure 7.9: State diagram for the M/M/1/K system.

Figure 7.10: An MIMIC system, for C = 3.

Figure 7.11: State transition diagram for an MIMIC system, for C = 3.

Figure 7.12: MIMIC loss system.

Figure 7.13: A three-stage closed queuing network.

Figure 7.14: State transition rate diagram for a simple closed system.

Figure 7.15: Arbitrary closed system.

Figure 7.16: Open system model.

Figure 7.17: Central server model.

Figure 7.18: G(k) grid calculation.

Figure 7.19: Network for mean variable analysis.

Chapter 8: Simulation Analysis

Figure 8.1: Projectile motion.

Figure 8.2: Continuous variable plot.

Figure 8.3: Basic model of GASP IV control.

Figure 8.4: GASP IV main FORTRAN program.

Figure 8.5: Subroutine Event for bank teller problem.

Figure 8.6: Subroutine Intlc for bank teller problem.

Figure 8.7: Arrival routine Event code.

Figure 8.8: End of service routine.

Figure 8.9: Basic GPSS modeling component blocks.

Figure 8.10: GPSS model for the bank teller problem.

Figure 8.11: GPSS code for the bank teller problem.

Figure 8.12: Simscript bank teller pension code.

Figure 8.13: Basic symbols and statements for Slam models.

Figure 8.14: Slam II bank teller problem network model.

Figure 8.15: Slam II bank teller problem code.

Figure 8.16: Assembly line example.

Figure 8.17: Slam II network model for the assembly line problem.

Figure 8.18: Queuing model of a distributed database system.

Figure 8.19: Slam II network simulation model for a distributed database system.

Figure 8.20: Slam II network model code.

Chapter 9: Petri Nets

Figure 9.1: Basic Petri net components.

Figure 9.2: Example perpetual motion Petri net.

Figure 9.3: Petri net example.

Figure 9.4: Dual of Petri Net from Figure 9.3.

Figure 9.5: Inverse of Petri Net from Figure 9.3.

Figure 9.6: Multipath arc.

Figure 9.7: Multipath arc as bold line.

Figure 9.8: Marked Petri net.

Figure 9.9: Enabled transition.

Figure 9.10: New Petri net state.

Figure 9.11: Resource sharing example.

Figure 9.12: Allocated resource.

Figure 9.13: Petri net with an inhibitor.

Figure 9.14: Reachability graph for the reader and writer problem.

Figure 9.15: Petri net component to test condition greater than M.

Figure 9.16: Petri net component to test condition equal but not greater than M.

Figure 9.17: Petri net modeling conflict.

Figure 9.18: Petri net component to test condition less than.

Figure 9.19: Petri net modeling concurrency.

Figure 9.20: Petri net modeling confusion.

Figure 9.21: Petri net indicating reachability and reversibility.

Figure 9.22: Deadlocked Petri net.

Figure 9.23: Timed Petri net.

Figure 9.24: Timed Petri net with conflict.

Figure 9.25: State transition timing graph.

Figure 9.26: Timed Petri net with immediate transitions.

Figure 9.27: Priority-based Petri net.

Figure 9.28: Timed and priority net.

Figure 9.29: Generalized Petri net.

Figure 9.30: Generalized Petri Net.

Chapter 10: Hardware Testbeds, Instrumentation, Measurement, Data Extraction, and Analysis

Figure 10.1: General testbed configuration.

Figure 10.2: Testbed node architecture.

Figure 10.3: Host software architecture.

Figure 10.4: IOP functional architecture.

Figure 10.5: Testbed/ISO correspondence.

Figure 10.6: Conceptual network server.

Figure 10.7: Message transmission times.

Figure 10.8: Mean queue length.

Figure 10.9: Mean response time.

Figure 10.10: Network utilization.

Figure 10.11: Mean system service time.

Figure 10.12: Pipeline effect on queue fall-through time.

Figure 10.13: Network throughput.

Figure 10.14: Network service time.

Chapter 11: System Performance Evaluation Tool Selection and Use

Figure 11.1: Typical response time measurement.

Figure 11.2: Transaction processing response partitioning.

Figure 11.3: Stretch factor compared with utilization.

Figure 11.4: Throughput curves versus response curves.

Figure 11.5: Multiprocessor efficiency curve.

Figure 11.6: Metrics versus usefulness.

Chapter 12: Analysis of Computer Architectures

Figure 12.1: Central server model.

Figure 12.2: Central server Petri net.

Figure 12.3: Multiple disk example Petri net.

Figure 12.4: Multiprocessor model using central processor.

Figure 12.5a: Shared memory model.

Figure 12.5b: Multibank shared memory model.

Figure 12.6: Multiprocessor system with N = 2 and M = 4.

Figure 12.7: Multiprocessor system with N = 2 and M = 2.

Figure 12.8: Probability state transition diagram.

Figure 12.9: Petri net model for multiprocessor system.

Chapter 13: Analysis of Operating System Components

Figure 13.1: Model for LINUX 7.2.

Figure 13.2: High-level model of CPU scheduler implemented in AWESIM.

Figure 13.3: AWESIM model for CPU scheduling.

Figure 13.4: High-level network model.

Figure 13.5: AWESIM model for Windows ME.

Figure 13.6: AWESIM model for Windows NT.

Chapter 14: Database Systems Performance Analysis

Figure 14.1: Oracle process and thread structure on NT.

Figure 14.2: Configurable pool database server.

Figure 14.3: Components of the database services address space.

Figure 14.4: Database Manager Shared Memory overview.

Figure 14.5: Logical versus physical view of the database.

Figure 14.6: Logical tablespace structures.

Figure 14.7: Informix versus Microsoft SQL Server.

Figure 14.8: Oracle versus Microsoft SQL Server.

Figure 14.9: Informix versus Oracle.

Chapter 15: Analysis of Computer Networks Components

Figure 15.1: Spectrum of computer system modeling techniques.

Figure 15.2: Scan blocks.

Figure 15.3: Another scan block.

Figure 15.4: Scan time versus message size, configuration 1.

Figure 15.5: Scan time versus message size, configuration 2.

Figure 15.6: Scan time versus message size, configuration 1b.

Figure 15.7: Scan time versus message size, configuration 2b.

Figure 15.8: Physical and logical numbering of interface units.

Figure 15.9: Token bus with three interface units.

Figure 15.10: Mapping logical to physical location.

Figure 15.11: Taxonomy of computer interconnection structures.

Figure 15.12: Local computer networks taxonomy.

Figure 15.13: Generalized distributed computer network.

Figure 15.14: General interconnection model.

Figure 15.15: Examples of interconnection structures.

Figure 15.16: ISO OSI model.

Figure 15.17: Basic components of a simulation model.

Figure 15.18: Basic structure of LAN simulator.

Figure 15.19: Functional components of a distributed processing system.

Figure 15.20: LAN evaluation metrics.

Figure 15.21: Simulated message flow graph.

Figure 15.22: Analysis module functional diagram.

Figure 15.23: Example performance evaluation plots.