Home Networking Basis: Transmission Environments and Wired/Wireless Protocols

All Ethernet transmission systems defined by the 802.3 standards share the same MAC protocol. The 802.3-defined MAC basically needs to know if the medium is free before the transmission and if there is a collision during the transmission. Therefore, different physical layers can be presented to the MAC through a common interface encompassing these sensing and transmission capabilities. A Media Independent Interface is defined in the Ethernet standards to separate the common MAC function from different physical layer transmission systems. This separation is very valuable to a multiple physical layer capable Ethernet transceiver as well as to the organization of technology development efforts. Besides these media-sensing and data-transmitting capabilities, a management interface is also defined as a part of the MII to enable functions such as autonegotiation.

The data transmitting capabilities of the MII include transmit clock, transmit enable, transmit error, and 4 bits of transmit data, in the transmit direction, and receive clock, receive enable, receive error, and 4 bits of receive data in the receive direction. Because the transmit and receive paths are separate, MII is capable of full-duplex operation. There are also a carrier sense pin and a collision detection pin defined for media sensing. For management purposes, a Management Data Clock (MDC) pin and a Management Data I/O (MDIO) pin are defined, but a 40-pin connector is also defined in case that physical layer and the MAC circuits are implemented separately. On this 40-pin connector, 4 power supply pins and 18 ground pins are also defined in addition to these 18 media sensing, data transmission, and management clock and I/O pins.

6.7.1 Data Interface

For the transmit path, the clock, TX_CLK, is supplied by the physical layer (PHY) and can be present all the time. Because the data path is 4 bits wide, the TX_CLK frequency is a quarter of the bit rate of a particular Ethernet transmission system (i.e., 2.5 MHz for 10BaseT and 25 MHz for 100BaseT4, 100BaseTX, and 100BaseT2). The transmit enable, TX_EN, coincides with the presence of data bits, TXD<3:0>, and they are all from the MAC. Meanwhile, the carrier sense, CRS, detects the same transmission on the media by the PHY and becomes active after a little delay as shown in Figure 6.90. Any transmission error detected by the PHY is relayed to the MAC over the TX_ER pin.

For the receive path, the clock, RX_CLK, can also be present all the time. The RX_CLK frequency should also be one fourth of the transmission throughput (i.e., 2.5 MHz for 10BaseT and 25 MHz for 100BaseT4, 100BaseTX, and 100BaseT2). The receive data valid, RX_DV, starts during the preamble and no later than the Start Frame Delimiter (SFD) as shown in Figure 6.91. Any receive error detected by the MAC is relayed to the PHY over the RX_ER pin. All receive path signals are from the PHY.

6.7.2 Management Interface

MDC is sent from the MAC to the PHY as the timing reference for transfer of information on the MDIO signal. MDC is an aperiodic signal that has no maximum high or low times. The minimum high and low times for MDC shall be 160 ns each, and the minimum period for MDC shall be 400 ns. MDIO is a bidirectional signal between the MAC and the PHY. It is used to transfer control information and status. Control information is driven by the MAC synchronously with respect to MDC and is sampled synchronously by the physical layer. Status information is supplied by the PHY synchronously with respect to MDC and is sampled synchronously by the MAC.

A management frame structure is defined in the standards for transferring information over the MDIO as shown in Figure 6.92. The IDLE condition on MDIO is a high-impedance state. At the beginning of each transaction, the MAC sends a sequence of 32 contiguous logic one bits of preamble, PRE, on MDIO with 32 corresponding cycles on MDC to provide the physical layer with a pattern that it can use to establish synchronization. A physical layer shall observe a sequence of 32 contiguous 1 bits on MDIO with 32 corresponding cycles on MDC before it responds to any transaction. The start of frame, ST, is indicated by a <01> pattern. This pattern ensures transitions from the default logic one line state to zero and back to one. The operation code, OP, for a read transaction is <10>, while the operation code for a write transaction is <01>. The physical layer address, PHYAD, is 5 bits, allowing the identification of 32 different physical layer entities. The register address, REGAD, is also 5 bits, allowing 32 individual registers to be addressed within each physical layer. The register accessed at zero <00000> is the control register, and the register accessed at one <00001> is the status register. The turnaround time, TA, is a 2-bit time spacing between the REGAD and DATA to avoid contention during a read transaction. For a read transaction, both the MAC and the PHY remain in a high-impedance state for the first bit time of the turnaround. The PHY drives a 0 bit during the second bit time of the turnaround. During a write transaction, the MAC drives a 1 bit for the first bit time of the turnaround and a 0 bit for the second bit time of the turnaround. The data field, DATA, is 16 bits.

The MII has been very well adapted by the Ethernet manufacturers such that a qualified stand-alone PHY device can be used in conjunction with any other qualified MAC components over this interface.