Wireless Communications Circuits and Systems (IEE Circuits, Devices and Systems Series 16)

Chapter 2: Non-Complex Signal Processing in a Low-IF Receiver

Table 2.1: Receiver characteristics

Chapter 3: A Reconfigurable Baseband Chain for 3G Wireless Receivers

Table 3.1: Measured performance of the reconfigurable chain blocks

Table 3.2: Results summary for different receiver configurations

Chapter 4: Field-Programmable and Reconfigurable Analogue and Mixed-Signal Arrays

Table 4.1: Commercial FPAAs

Chapter 5: A Low-Power, Low-Voltage Bluetooth Channel Filter Using Class AB CMOS Transconductors

Table 5.1: Single-ended design values of Bluetooth channel filter

Table 5.2: Simulated performance of channel filter (nominal processing)

Table 5.3: Typical simulated performance of transconductor and channel filter with normal (k_p/k_n = 1) and skewed (k_p/k_n = 1.2) MOSTs

Chapter 7: Low-Voltage Integrated RF CMOS Modules and Frontend for 5 GHz and Beyond

Table 7.1: LNA performance summary in this work

Table 7.2: Summary of the process characteristics, and performances of the two VCOs

Table 7.3: Measured receiver performance

Chapter 8: Design of Integrated CMOS Power Amplifiers for Wireless Transceivers

Table 8.1: Example of some digital wireless standards

Table 8.2: Example of reported CMOS power amplifiers

Chapter 9: Parasitic-Aware RF IC Design and Optimisation

Table 9.1: Relationships between probability of hill climbing and parameters Temp and oldcost-cost (Δcost)

Table 9.2: Summary of the 22 design parameter values before and after optimisation (see Figure 9.20)

Table 9.3: Summary of output power, drain efficiency and gain before and after optimisation of the three-stage RF power amplifier

Table 9.4: Summary of the 11 design parameters before optimisation and after optimisation with a distributed amplifier (see Figure 9.24)

Table 9.5: Summary of bandwidth, gain and gain flatness before optimisation and after optimisation with distributed amplifier

Chapter 10: Testing of RF, Analogue and Mixed-Signal Circuits for Communications—an Embedded Approach

Table 10.1: Performance summary of integrated prototypes