Wireless Communications Circuits and Systems (IEE Circuits, Devices and Systems Series 16)

4.8 References

  1. Sivilotti, M. A.: ‘A dynamically configurable architecture for prototyping analog circuits’. Proceedings of Decennial Caltech Conference on Advanced Research in VLSI, Cambridge, MA, March 1988, pp. 237–58

  2. Gaudet, V. C. and Gulak, P. G.: ‘Implementation issues for high-bandwidth field-programmable analog arrays’. Journal of Circuits, Systems and Computers, 2000, 8 (5), pp. 541–58

  3. Looby, C. A. and Lyden, C.: ‘Op-amp based CMOS field-programmable analogue array’. IEE Proceedings: Circuits, Devices and Systems, April 2000, 147 (2), pp. 93–9

  4. Lee, E. K. F. and Gulak, P. G.: ‘A CMOS field programmable analog array’, IEEE Journal of Solid-State Circuits, December 1991, 26 (12), pp. 1860–67

  5. Lee, E. K. and Gulak, P. G.: ‘A transconductor-based field-programmable analog array’. IEEE International Solid-State Circuits Conference Digest, San Francisco, CA, USA, February 1995, pp. 198–99

  6. Embabi, S. H. K., Quan, X., Oki, N., Manjrekar, A. and Sanchez-Sinencio, E.: ‘A field programmable analog signal processing array’. Proceedings of IEEE Midwest Symposium on Circuits and Systems, Puebla, August 1996, pp. 151–54

  7. Quan, X., Embabi, S. H. K. and Sanchez-Sinencio, E.: ‘A currentmode based field programmable analog array architecture for signal processing applications’. Proceedings of IEEE Custom Integrated Circuits Conference, Santa Clara, 1998, pp. 12.6.1–12.6.4

  8. Deakin, S. J. and Hatfield, J.: ‘A field programmable current-mode analog VLSI'. Proceedings of IEE Symposium on Analogue Signal Processing, Oxford, November 1996, pp. 6/1–6/6

  9. Pierzchala, E. and Perkowski, M. A.: ‘High-speed field programmable analog array architecture design’. Proceedings of ACM/SIGDA FPGA’94, Berkeley, CA, USA, February 1994

  10. Pierzchala, E., Perkowski, M., Vanhalen, P. and Schaumann, R.: ‘Current-mode amplifier/integrator for a field programmable analog array’. IEEE International Solid-State Circuits Conference Technical Digest, San Francisco, February 1995, pp. 196–97

  11. Kutuk, H. and Kang, S. M.: ‘A field-programmable analog array (FPAA) using switched-capacitor technique’. Proceedings of IEEE International Symposium on Circuits and Systems, Atlanta, May 1996, 4, pp. 41–43

  12. Klein, H. W.: ‘The EPAC architecture: an expert cell approach to field programmable analog devices’. Proceedings of ACM/SIGDA FPGA’96, Monterey, CA, 1996, pp. 94–8

  13. Bratt, A. and Macbeth, I.: ‘Design and implementation of a field programmable analogue array’. Proceedings of ACM/SIGDA FPGA’96, Monterey, CA, 1996, pp. 88–93

  14. Anderson, D., Marcjan, C., Bersch, D., Anderson, H., Hu, P., Palusinski, O., Gettman, D., Macbeth, I. and Bratt, A.: ‘A field programmable analog array and its application’. IEEE Custom Integrated Circuits Conference, Santa Clara, 1997, pp. 555–58

  15. Gaudet, V. C. and Gulak, P. G.: ‘CMOS implementation of a current conveyor-based field-programmable analog array’ (University of Toronto, 1998), pp. 1156–59

  16. Chang, S. T., Hayes-Gill, B. R. and Paul, C. J.: ‘Multifunction block for a switched-current field programmable analogue array’. Proceedings of IEEE Midwest Symposium on Circuits and Systems, Ames, Iowa, August 1996, 1, pp. 8–16

  17. Bozic, M. and Grundy, D. L.: ‘A novel approach to VLSI analogue design’. Proceedings of IEE Symposium on Analogue Signal Processing, Oxford, 1996, pp. 10/1–10/6

  18. Pankiewicz, B., W jcikowski, M., Szczepanski, S. and Sun, Y.: ‘A CMOS field programmable analog array and its application in continuous-time OTA-C filter design'. Proceedings of IEEE International Symposium on Circuits and Systems, Sydney, May 2001, 1, pp. 5–8

  19. Pankiewicz, B., W jcikowski, M., Szczepa ski, S. and Sun, Y.: ‘A CMOS field programmable analog array for continuous-time OTA-C filter applications’, IEEE Journal of Solid-State Circuits, February 2002, 147 (2), pp. 125–36

  20. Loh, K. H., Hiser, D. L., Adams, W. J. and Geiger, R. L.: ‘A versatile digitally controlled continuous-time filter structure with wide range and fine resolution capability’, IEEE Transactions on Circuits and Systems-II, 1992, 39, pp. 265–76

  21. MOTOROLA, ‘MPAA020 field programmable analog array datasheet’. April 1997

  22. IMP Inc, ‘Preliminary Product Information – IMP50E10 EPAC (Electrically programmable analog circuit)’. Datasheet, 1995; EPAC Design Handbook, April 1996

  23. Lattice Semiconductor, Programmable analogue circuits (ispPAC). [Online] http://www.latticesemi.com

  24. Zetex Semiconductors, TRAC (Totally Reconfigurable Analogue Circuit). [Online]. http://www.zetex.com

  25. Anadigm Company, The AN10E40 field programmable analog array. [Online]. http://www.anadigm.com

  26. SIDSA Company, FIPSOC mixed signal system on chip. [Online]. http://www.fipsoc.com

  27. Altera Company, SoPC Information [Online], http://www.altera.com

  28. Toumazou, C., Lidgey, F. J. and Haigh, D. G. (Eds.): ‘Analogue IC design: the current-mode approach’ (Peter Peregrinus, London, 1990)

  29. Laker, K. R. and Sansen, W.: ‘Design of analog integrated circuits and systems’ (McGraw-Hill, 1994)

  30. Johns, D. A. and Martin, K.: ‘Analog integrated circuit design’ (John Wiley, New York, 1997)

  31. Sanchez-Sinencio, E. and Andreou, A. G. (Eds.): ‘Low-voltage/lowpower integrated circuits and systems’ (IEEE Press, Piscataway, New Jersey, 1999)

  32. Tsividis, Y. and Voorman, J. O. (Eds.): ‘Integrated continuous-time filters’ (IEEE Press, Piscataway, New Jersey, 1993)

  33. Schaumann, R., Laker, K. R. and Ghausi, M. S.: ‘Active filter design: passive, active and switched-capacitor’ (Prentice Hall, Englewood Cliffs, New Jersey, 1990)

  34. Deliyannis, T., Sun, Y. and Fidler, J. K.: ‘Continuous-time active filter design’ (CRC Press, Florida, USA, January 1999)

  35. Sun, Y.: ‘Design of high frequency integrated analogue filters’ (IEE, Stevenage, UK, 2002)

  36. Sun, Y.: Guest Editor, ‘Special issue on high-frequency integrated analogue filters’, IEE Proceedings: Circuits, Devices and Systems, February 2000, 147 (1), pp. 1–90

  37. Schaumann, R. and Karsilayan, A. I.: ‘On-chip automatic tuning of filters’, Chapter 7, in Sun, Y. (Ed.): ‘Design of high frequency integrated analogue filters’ (IEE, Stevenage UK, 2002)

  38. Moritz, J. R. and Sun, Y.: ‘Tuning of multiple loop feedback leapfrog bandpass filters’, Electronics Letters, 2001, 37 (11), pp. 671–72

  39. Moritz, J. R. and Sun, Y.: ‘Automatic tuning of high-frequency high-Q multiple loop feedback bandpass filters’. Proceedings of IEEE International Symposium on Circuits and Systems, Arizona, USA, May 2002

  40. Hughes, J. B., Worapishet, A. and Sitdhikorn, R.: ‘Low voltage techniques for switched-current filters’, Chapter 5, in Sun, Y. (Ed.): ‘Design of high frequency integrated analogue filters’ (IEE, Stevenage, UK, 2002)

  41. Frey, D.: ‘Log Domain Filters’, Chapter 4, in Sun, Y. (Ed.): ‘Design of high frequency integrated analogue filters’ (IEE, Stevenage, UK, 2002)

  42. Banu, M. and Tsividis, Y.: ‘MOSFET-C techniques: designing power efficient high frequency filters’, Chapter 2, in Sun, Y. (Ed.): ‘Design of high frequency integrated analogue filters’ (IEE, Stevenage, UK, 2002)

  43. Groenevold, G.: ‘Low-power MOSFET-C 120MHz Bessel allpass filter with extended tuning range’, IEE Proceedings: Circuits, Devices and Systems, 2000, 147 (1), pp. 28–34

  44. He, Y., Jiang, J. and Sun, Y.: ‘CMOS R-MOSFET-C fourth-order Bessel filter with accurate group delay’, Proceedings of IEEE International Symposium on Circuits and Systems, Arizona, USA, May 2002

  45. Sun, Y. and Hill, C.: ‘Low power fully differential CMOS filter for video frequencies’, IEEE Transactions on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 2001, 48 (12), pp. 1144–48

  46. Sanchez-Sinencio, E. and Silva-Martinez, J.: ‘CMOS transconductance amplifiers, architectures and active filters: a tutorial’, IEE Proceedings: Circuits, Devices and Systems, 147 (1), 2000, pp. 3–12

  47. Glinianowicz, J., Jakusz, J., Szczepanski, S. and Sun, Y.: ‘A high frequency two-input CMOS OTA for continuous-time filter applications’, IEE Proceedings: Circuits, Devices and Systems, 2000, 147 (1), pp. 13–18

  48. Sun, Y., Hill, C. and Szczepanski, S.: ‘Large dynamic range high frequency fully differential CMOS transconductance amplifier’, International Journal of Analog Integrated Circuits and Signal Processing, March 2003, 34 (3), pp. 247–55

  49. Sun, Y.: ‘Architectures and design of OTA/gm-C filters’, Chapter 1, in Sun, Y. (Ed.): ‘Design of high frequency integrated analogue filters’ (IEE, Stevenage, UK, 2002)

  50. Sanchez-Sinencio, E. and Smith, S. L.: ‘Continuous-time low-voltage current-mode filters’, Chapter 11, in Sanchez-Sinencio, E. and Andreou, A. G. (Eds.): ‘Low-voltage/low-power integrated circuits and systems’ (IEEE Press, Piscataway, New Jersey, 1999)

  51. Han, G. and Sanchez-Sinencio, E.: ‘CMOS transconductance multipliers: a tutorial’, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1998, 45, pp. 1550–63

  52. Pankiewicz, B., Szczepanski, S. and Sun, Y.: ‘CMOS level shifter and four quadrant analog mulitplier’. Proceedings of 9th International Conference on Mixed Design of Integrated Circuits and Systems, Wroclaw, Poland, June 2002

  53. Linares-Barranco, B., Rodriguez-Vazquez, A., Sanchez-Sinencio, E. and Huertas, J. L.: ‘Generation, design and tuning of OTA-C high-frequency sinusoidal oscillators’, IEE Proceedings-G, 1992, 139(5), pp. 557–68

  54. Sanchez-Sinencio, E., Ramirez-Angulo, J., Linares-Barranco, B. and Rodriguez-Vazquez, A.: ‘Operational transconductance amplifierbased nonlinear function synthesis’, IEEE Journal of Solid-State Circuits, 1989, 24 (6), pp. 1576–85

  55. Linares-Barranco, B., Sanchez-Sinencio, E., Rodriguez-Vazquez, A. and Huertas, J. L.: ‘A modular T-mode design approach for analog neural network hardware implementations’, IEEE Journal of Solid-State Circuits, 1992, 27 (5), pp. 701–13

  56. Thapar, H., Lee, S. S., Conroy, C., Contreras, R., Yeung, A., Chern, J.G., Pan, T. and Shih, S. M.: ‘Hard disk drive read channels: technology and trends’. Proceedings of IEEE Custom Integrated Circuits Conference, Santa Clara, 1998, pp. 309–16

  57. Su, H. and Sun, Y.: ‘A CMOS 100MHz continuous-time seventh-order 0.05 equiripple linear phase leapfrog multiple loop feed back gm-C filters’. Proceedings of IEEE International Symposium on Circuits and Systems, Arizona, May 2002

  58. Razavi, B.: ‘Challenges in portable RF transceiver design’, IEEE Circuits and Devices Magazine, September 1996, pp. 12–25

  59. Abidi, A.: ‘Low-power radio-frequency IC's for portable communications’, Proceedings of the IEEE, April 1995, 83 (4), pp. 544–69,

  60. Sun, Y.: Guest Editor, ‘Special Issue on RF Circuits and Systems for Wireless Communications', IEE Proceedings: Circuits, Devices and Systems, 2000, 149(5), pp. 321–75

  61. Colsell, S.: and Edwards, R.: ‘A comparative study of reconfigurable digital and analogue technologies for future mobile communication systems’. Proceedings of IEE International Conference 3G Mobile Communication Technologies, London, March 2001, pp. 302–5

  62. Hollaman, T., Lindfors, S., Salo, T., Lansirinne, M. and Halo-Nen, K.: ‘A 2.7 CMOS dual-mode basedband filter for GSM and WCDMA’. Proceedings of IEEE ISCAS, Sydney, Australia, 2001, pp. I-316–9

  63. Alzaher, H. A., Elwan, H. O. and Ismail, M.: ‘A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers’, IEEE Journal of Solid-State Circuits, 2002, 37 (1), pp. 27–37

  64. Elwan, H., Alzaher, H. and Ismail, M.: ‘A new generation of global wireless compatibility’, IEEE Circuits and Devices Magazine, January, 2001, pp. 2–19

  65. Elwan, H., Ravindran, A. and Ismail, M.: ‘A CMOS low power baseband chain for a GSM/DECT multistandard receiver’, IEE Proceedings: Circuits, Devices and Systems, 2002, 149 (5), pp. 337–47

  66. Li, D. and Tsividis, Y.: ‘Active filters using integrated inductors’, Chapter 3, in Sun, Y. (Ed.): ‘Design of high frequency integrated analogue filters’ (IEE, Stevenage, UK, 2002)

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