Wireless Communications Circuits and Systems (IEE Circuits, Devices and Systems Series 16)

10.9 References

  1. ‘The international technology roadmap for semiconductors’ (Semiconductor Industry Association, 2001 Edition)

  2. Rabaey, J.: ‘Digital integrated circuits: a design perspective’ (Englewood Cliffs, New Jersey: Prentice Hall, 1996)

  3. Roberts, G. W.: ‘Metrics, techniques, and recent developments in mixed-signal testing’, Digest of technical papers. IEEE International Conference on Computer-Aided Design, San Jose, 1996, pp. 10–14

  4. Razavi, B.: ‘RF microelectronics’ (Prentice Hall, Englewood Cliffs, New Jersey, 1998)

  5. Kenington, P. B.: ‘Emerging technologies for software radio’, IEE Electronics and Communication Engineering Journal, April 1999, 11 (2), pp. 69–83

  6. Burns, M. and Roberts, G. W.: ‘An introduction to mixed-signal IC test and measurement’ (Oxford University Press, New York, 2001)

  7. Milor, L. S.: ‘A tutorial introduction to research on analog and mixed-signal circuit testing’, IEEE Transactions on Circuits and Systems – II: Analog and Digital Signal Processing, October 1998, 45 (10), pp. 1389–407

  8. Huss, S. D. and Gyurcsik, R. S.: ‘Optimal ordering of analog integrated circuit tests to minimize test time’. Proceedings of IEEE Design Automation Conference, San Francisco, 1991, pp. 494–99

  9. Milor, L. and Sangiovanni-Vincentelli, A. L.: ‘Minimizing production test time to detect faults in analog circuits’. IEEE Transactions on Computer-Aided Design of Integrated Circuits, June 1994, 13 (6), pp. 796–813

  10. Milor, L. and Sangiovanni-Vincentelli, A. L.: ‘Optimal test set design for analog circuits’. Proceedings of IEEE International Conference on Computer-Aided Design, Santa Clara, 1990, pp. 294–97

  11. Souders, T. M. and Stenbakken, G. N.: ‘Cutting the high cost of testing’, IEEE Spectrum, March 1991, 28 (3), pp. 48–51

  12. Maly, W., Strojwas, A. J. and Director, S. W.: ‘VLSI yield prediction and estimation: a unified framework’, IEEE Transactions on Computer-Aided Design of Integrated Circuits, January 1986, 5 (1), pp. 114–30

  13. Nagi, N., Chatterjee, A. and Abraham, J. A.: ‘Fault simulation of linear analog circuits’, Journal of Electronic Testing: Theory and Applications, 1993, 4, pp. 345–60

  14. Sachdev, M. and Atzema, B.: ‘Industrial relevance of analog IFA: a fact or a fiction’. Proceedings of IEEE International Test Conference, Washington, DC, October 1995, pp. 61–70

  15. Chao, C. Y., Lin, H. J. and Milor, L.: ‘Optimal testing of VLSI analog circuits’, IEEE Transactions on Computer-Aided Design of Integrated Circuits, January 1997, 16 (1), pp. 58–77

  16. Temes, G. C.: ‘Efficient methods of fault simulation’. Proceedings of IEEE Midwest Symposium on Circuits and Systems, Lubbot, TX, 1977, pp. 191–94

  17. Zwolinski, M., Brown, A. D., Chalk, C. D.: ‘Concurrent analog fault simulation’. Proceedings of IEEE International Mixed-Signal Test Workshop, Seattle, June 1997, pp. 42–47

  18. Tian, M. W. and Shi, R.: ‘Efficient DC fault simulation of nonlinear analog circuits’. Proceedings of IEEE Design, Automation and Test in Europe Conference, Paris, 1998, pp. 899–904

  19. Huynh, S. D., Kim, S., Soma, M. and Zhang, J.: ‘Automatic analog test signal generation using multifrequency analysis’, IEEE Transactions on Circuits and Systems – II: Analog and Digital Signal Processing, 46 (5), May 1999, pp. 565–75

  20. Devarayanadurg, G., Soma, M., Goteti, P. and Huynh, S. D.: ‘Test set selection for structural faults in analog IC's’, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, July 1999, 18 (7), pp. 1026–38

  21. Grochowski, A., Bhattacharya, D., Viswanathan, T. R. and Laker, K.: ‘Integrated circuit testing for quality assurance in manufacturing: history, current status, and future trends’, IEEE Transactions on Circuits and Systems – II: Analog and Digital Signal Processing, August 1997, 44 (8), pp. 610–33

  22. Helmreich, K.: ‘Test path simulation and characterization’. Proceedings of IEEE International Test Conference, Baltimore, MD, 2001, pp. 415–23

  23. Roberts, G. W.: ‘Improving the testability of mixed-signal integrated circuits’. Proceedings of IEEE Custom Integrated Circuits Conference, Santa Clara, 1997, pp. 214–21

  24. Hawrysh, E. M. and Roberts, G. W.: ‘An integration of memory-based analog signal generation into current DFT architectures’. Proceedings of IEEE International Test Conference, Washington, DC, 1996, pp. 528–37

  25. Dufort, B. and Roberts, G. W.: ‘On-chip analog signal generation for mixed-signal built-in self-test’, IEEE Journal of Solid-State Circuits, March 1999, 34 (3), pp. 318–30

  26. Mahoney, M. V.: ‘DSP-based testing of analog and mixed-signal circuits’ (IEEE Computer Society Press, Washington, DC, 1987)

  27. Schreier, R.: ‘An empirical study of high-order single-bit delta-sigma modulators’, IEEE Transactions on Circuits and Systems – II: Analog and Digital Signal Processing, August 1993, 40 (8), pp. 461–6

  28. Hafed, M., Abaskharoun, N. and Roberts, G. W.: ‘A 4-GHz effective sample-rate integrated test core for analog and mixed-signal circuits’, IEEE Journal of Solid-State Circuits, April 2002, 37 (4), pp. 499–514

  29. Hajjar, A. and Roberts, G. W.: ‘A high speed and area efficient on-chip analog waveform extractor’. Proceedings of IEEE International Test Conference, 1998, pp. 688–97

  30. Lofstrom, K.: ‘Early capture for boundary scan timing measurements’. Proceedings of IEEE International Test Conference, Washington, DC, 1996, pp. 417–22

  31. Hafed, M., Laberge, S. and Roberts, G. W.: ‘A robust deep submicron programmable DC voltage generator’. Proceedings of IEEE International Symposium on Circuits and Systems, Geneva, 2000, 4, pp. 5–8

  32. Laberge, S.: ‘DC voltage generation using periodic bit-stream modulation’. Masters Thesis, McGill University, 2002

  33. Hsieh, L. and Kumar, S. P.: ‘Digitizer error extraction in the nonlinearity test’. Proceedings of IEEE International Test Conference, Washington, DC, 1994, pp. 757–62

  34. Song, B., Lee, S. and Tompsett, M.: ‘A 10-b 15-MHz CMOS recycling two-step A/D converter’, IEEE Journal of Solid-State Circuits, December 1990, 25 (6), pp. 1328–38

  35. Razavi, B.: ‘Principles of data conversion system design’ (IEEE Press, Washington, DC, 1995)

  36. Poulton, K., Neff, R., Muto, A., Liu, W., Burstein, A. and Heshami, M.: ‘A 4GSample/S 8b ADC in 0.35 μm CMOS’, Digest IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 166–67

  37. Kulp, B. D.: ‘Testing and characterizing jitter in 100 Base-Tx and 155.52 Mbits/s ATM devices with 1 Gsample/s AWG in an ATE system'. Proceedings of IEEE International Test Conference, Washington, DC, 1996, pp. 104–11

  38. Abaskharoun, N., Hafed, M. and Roberts, G. W.: ‘Strategies for on-chip sub-nanosecond signal capture and timing measurement’. Proceedings of IEEE International Symposium on Circuits and Systems, Sydney, 2001, 4, pp. 174–77

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