HyperTransportв„ў System Architecture

The Previous Chapter

HyperTransport uses PCI configuration. The previous chapter described HyperTransport technology configuration for host bridges, tunnels, and end (cave) devices. These devices use the type 0 configuration header format, while HyperTransport-to-HyperTransport bridges and bridges between HyperTransport and other PCI compatible protocols (e.g. PCI and PCI-X) use the type 1 header format and are described separately in Chapter 16, entitled "HyperTransport Bridges," on page 407. Many aspects of HyperTransport device configuration are exactly the same as for generic PCI devices, although some header fields are used differently in HyperTransport, and some not at all. Devices also require at least one HyperTransport-specific advanced capability register block in addition to the basic PCI configuration space header fields.

This Chapter

The high speed signaling performed by HT devices is based on point-to-point differential signaling and source synchronous clocking. Details associated with link power requirements and the driver and receiver characteristics are discussed in this chapter. Also, the characteristics of the system- related signals, including RESET#, PWROK, LDTSTOP#, and LDTREQ# are discussed.

The Next Chapter

The next chapter focuses on the source synchronous clocking environment within HT. This involves the use of the source synchronous transmit clock to load data into a receive FIFO and the transfer of data into the receiver time domain with a receive clock that unloads data from the FIFO. Additionally, the specification defines three clocking modes that require different levels of support for passing packets between these two clock domains.