HyperTransportв„ў System Architecture

This section defines the timing parameters for CAD[n:0], CTL, and CLK[m:0].

The HyperTransport link uses a simple timing methodology that accounts for simultaneous worst case combinations of uncertainties. This timing methodology attempts to cover all cases that could occur in operational systems, and is defined to provide zero additional margin. This means that board designers and designers of device transmitter and receiver interfaces must meet specification requirements over all process, voltage, and temperature corner cases.

Differential Signal Skew

The maximum skew allowed by the output driver between the true signal and its differential complement is defined as T _ODIFF. Figure 14-10 on page 380 illustrates this parameter, which is measured at the mid-point of the transition of the differential signal with respect to ground (i.e., the common-mode point). The maximum skew allowed is limited by Delta-V _OCM being within specification.

T _IDIFF is also defined by the specification, which is the maximum skew allowed at the input of the receiver. Specifically, T _IDIFF defines the max skew allowed between the true signal and its differential complement measured at the mid-point of the transition of the signal which is input to a receiver. The measurement for T _IDIFF is made in the same manner as for T _ODIFF. Table 14-11 on page 380 lists maximum skew permitted at the output of the driver and for the input of the receiver at various transmission rates.

Table 14-11. Maximum Differential Output and Input Skew Values

Source Synchronous Clock Skew

The source synchronous clocking employed by HT requires that CLKOUT be delayed by one-half bit time to align the clock edge in the center of the CADOUT and CTLOUT bit time. This represents a 90 degree phase shift on clock relative to the CADOUT and CTLOUT signals. Similarly, the specification defines the maximum skew permitted at the receiver between CLKIN and CADIN or CTLIN. The specification permits some tolerance in the clock delay relative to CAD and CTL for both the driver output and receiver input.

Source Synchronous Clock Skew at the Transmitter

The specified parameter for the output measurement is called CAD valid time (T _CADV ). Figure 14-11 on page 382 illustrates the relationship between CLKOUT and CADOUT or CTLOUT. An example of this relationship is discussed below:

Assuming an 800MHz clock (which yields 1600MT/s), the clock period is 1250ps, and the bit-time period (TBIT) is 625ps. When CADOUT[n:0] or CTLOUT is driven, the CLKOUT signals should be driven one-half bit time later (TCADV_typical = 312.5ps). The margin of skew allowed between CLKOUT and CADOUT[n:0] or CTLOUT is a function of the uncertainties related to the transmitter PHY, transmitter package skew, and transmitter clock. The minimum and maximum values are defined below:

• T _{CADV_min} (CAD valid time) is the smallest time allowed between the CADOUT[n:0] or CTLOUT differential crossing point and CLKOUT differential crossing point measured at the driver. It is also the smallest time allowed between CLKOUT crossing point and CADOUT[n:0] or CTLOUT differential crossing point measured at the driver.

• T _{CADV_max} is the longest time allowed between CADOUT[n:0] or CTLOUT differential cross-over point and CLKOUT differential crossing point measured at the driver. It is also the longest time allowed between CLKOUT crossing point and CADOUT[n:0] or CTLOUT differential crossing point measured at the driver.

Table 14-12 on page 382 lists the permitted values for T _CADV.

Table 14-12. Source Synchronous CLK Output Skew Values

Source Synchronous Clock Skew at the Receiver

At the receiver end, source synchronous clock skew is affected by motherboard PCB skew. The PCB CLK trace length and median of the associated CAD/CLK length must be matched so that setup and hold time for CAD/CLK signals are not violated at the receiver. Realistically, the specification allows for some motherboard skew between CAD/CTL and its associated CLK signal. Two factors contribute to this skew:

1. Route length miss -match

2. Transmission line effects which are time-variant

The source synchronous clock skew parameter at the receiver is termed CAD valid time at receiver (T _CADVRS ).

• T _CADVRS is the CADIN/CTLIN valid time to CLKIN measured at the receiver inputs and includes PCB skew.

  (T _CADVRS = T _{CADV_min} - PCB Skew/2)

  (T _CADVRS = T _{CADV_max} + PCB Skew/2)

• T _CADVRH is the CADIN/CTLIN valid time from CLKIN measured at the receiver inputs and includes PCB skew. This is the time left over at the receiver after the CLK crossing point till the CAD/CTL crossing point. This time must be greater than the hold time.

T _CADVRS and T _CADVRH are measured at the receiver over a large number of samples and conditions which maximizes PCB skew. Table 14-13 on page 383 lists the minimum and maximum skew values.

Table 14-13. Source Synchronous CLK Input Skew Values

Setup and Hold Timing

Figure 14-12 on page 384 illustrates the setup and hold timing parameters and Table 14-14 on page 385 specifies the values at different transmission rates. The parameters are defined as follows :

• T _SU setup time is the required amount of time that the CAD[n:0] or CTL signals must be valid for prior to CLK transition crossing point at the receiver in order for the signal to be internally sampled correctly. T _SU is measured from the crossing point of the last CADIN transition to the CLKIN transition crossing point. T _SU maximum is specified to limit the amount of setup time that a device can require.

• T _HD hold time is the required amount of time that the CAD[n:0] or CTL signals must be valid for after CLK transition crossing point at the receiver in order for the signal to be internally sampled correctly. T _HD is measured from the crossing point of the earliest CADIN transition to the CLKIN transition crossing point. T _HD maximum is specified to limit the amount of hold time that a device can require.

Table 14-14. Setup and Hold Times for CAD and CTL