HyperTransportв„ў System Architecture
Chapter 20. I/O Compatibility
The Previous Chapter The previous chapter summarized some of the major additions to the HyperTransport protocol which will be forthcoming in Release 1.05 and Release 1.1 of the specification. Collectively, these additions are referred the HyperTransport Networking Extensions, and target some of the special requirements of communications processing. Key features include a message passing protocol for larger packets, a formal definition for switch devices, a link-level error recovery method, sixteen optional additional posted write virtual channels with defined arbitration and bandwidth allocation, direct peer-peer transfers, an increase in the number of outstanding transactions for host bridges, and a 64-bit addressing option. This Chapter HT is designed to support a variety of I/O and processor buses via bridges. The specification defines specific requirements for supporting PCI, PIC-X, AGP, and processor buses. This chapter discusses these support requirements. The Next Chapter The large 1 Terabyte HT address space may be outside the limits of a given processor or expansion bus. When address locations are mapped into the HT space that exceed the processor or expansion bus address space then the addresses must be remapped to/from HT space. The next chapter discusses the HT solution for remapping prefetchable memory, MMIO, and I/O addresses. |