HyperTransportв„ў System Architecture

An HT-based system may include processors or expansion buses that have smaller address ranges than the large 1 TeraByte space used by HT. In such cases address translation may be required. For example, the x86 CPU might have a maximum memory address range of 64GB and a PCI bus implementation may be limited to 4GB of memory address space. If addresses are allocated in HT address space beyond the range of the CPU and Expansion bus, then address translation is required.

To illustrate the possible remapping requirement, Figure 21-1 on page 479 depicts an implementation similar to that described in the previous paragraph. This example does not depict a typical implementation, but rather illustrates an extreme case where address remapping is required by both the CPU to HT Bridge and the HT-to-PCI Bridge. The system allocates a 4GB range of processor memory address space for PCI devices that is near the top of the 64GB range. This processor address space is mapped into the HT space above the 64GB range of the processor and beyond the address range of the PCI bus. When software executing on the CPU accesses a memory location within a PCI device two address translations must occur:

1. The CPU to HT Bridge must translate the CPU address within the 60 - 64GB address range to the 1,008 to 1,012GB range.

2. The HT-to-PCI Bridge must translate the HT address down to the 0-4GB range of the PCI bus.

A similar address translation must take place to support I/O address space. HT maps I/O space very high in its address space and outside the range of both the CPU and PCI bus, thereby creating the need for address remapping.

HT provides an Address Remapping Capability Block that support remapping HT addresses to expansion buses. However, the specification does not define a mechanism for remapping CPU to HT address space.