HyperTransportв„ў System Architecture

This capability block allows software to control the HT to expansion bus bridge address for:

  • remapping HT I/O address space down to a lower range within an expansion bus.

  • remapping HT MMIO space to expansion bus address space.

  • remapping HT Memory space to expansion bus address space.

  • remapping Bus Master memory transactions from expansion bus address space to HT address space.

Figure 21-2 on page 479 illustrates the format of the Address Remapping capability block. The following sections describe each register and its remapping function.

Figure 21-2. Format of the Address Remapping Capability Block

The registers within the remapping capability block are briefly described below. Detailed discussion of their implementation is discussed in the following sections.

  • Number of DMA Mappings ” This read-only field indicates how many DMA Primary/Secondary register sets (if any) are defined by the remapping capability block.

  • I/O Size ” This register is intended to permit configuration software to limit the I/O address range supported by the expansion bus to a range smaller than the 32MBs supported by HT.

  • Mapping Type ” The HT specification does not currently define a mapping type. This read-only register must be zero (0) and is reserved for future extensions.

  • Capability Type ” A read-only value of 01000b indicates an address remapping capability block.

  • Secondary Bus Non-Prefetchable Window Base ” This register is written by configuration software to define the HT address range that is mapped to MMIO space on the secondary (expansion) bus. Contents of this register are address bits 39:20, providing a minimum HT range of 1MB for expansion bus MMIO addresses.

  • SBNPCtl ” This register permits software to enable/disable the Secondary Bus Non-Prefetchable Window Base register. When the window register is enabled, the SBNPCtl register also specifies which HT attributes are supported by the expansion bus. (i.e. HT requests passing through the window may have these attributes active). The attributes include NonCoherent, Isochronous, and Compatibility.

  • Secondary Bus Prefetchable Window Base ” This register is written by configuration software to define the HT address range that is mapped to prefetchable memory address space on the secondary (expansion) bus. Contents of this register are address bits 39:20, providing a minimum HT range of 1MB for expansion bus prefetchable memory addresses.

  • SBPreCtl ” This register permits software to enable/disable the Secondary Bus Prefetchable Window Base register. When the window register is enabled, the SBPreCtl register also specifies which HT attributes are supported by the expansion bus. The attributes include NonCoherent, Isochronous, and Compatibility.

  • DMA Primary Base 1-N ” The DMA Primary Base register permits configuration software to define the HT base address (bits 39:24) for each DMA mapping. These mappings are used by bus masters residing on the expansion bus when accessing HT address space that is outside the range of the expansion bus.

  • DMACtl 1-N ” This register permits software to enable/disable the corresponding DMA mapping. When the mapping is enabled, the DMACtl register also specifies whether NonCoherent and Isochronous transactions are supported on the expansion bus.

  • DMA Secondary Base 1-N and DMA Secondary Limit 1-N ” These registers create a DMA memory window within the secondary (expansion) bus address range for DMA transfers to HT address space. The starting address of the HT range is specified by the DMA Primary Base register.

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