HyperTransportв„ў System Architecture

[SYMBOL] [A] [B] [C] [D] [E] [F] [G] [H] [I] [L] [M] [N] [O] [P] [R] [S] [T] [U] [V] [W] [X]

Data Coherency  

Data Packet   2nd   3rd   4th   5th   6th  

Data Packet Types  

Direct Memory Access   2nd  

Directed Requests   2nd   3rd   4th  

DMA Primary Base Register  

DMA Remapping  

DMA Secondary Base and Limit Registers  

DMA Transactions  

DMA Transfers  

DMA Window Control Register  

Double-Host Chain Initialization  

Double-Hosted Chain   2nd   3rd   4th   5th   6th   7th  

Double-Hosted Chain Ordering  

Downstream Ordering Rules   2nd  

Dword Read   2nd   3rd   4th   5th  

Dword Write  

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