HyperTransportв„ў System Architecture
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Packet Framing Packet Rejection 2nd Packetized Transfers PassPW Bit 2nd 3rd 4th 5th PCI Ordering 2nd PCI-X Ordering Peer-to-Peer 2nd 3rd 4th 5th Point-to-Point Interconnect Posted Request 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th Posted Sized Writes Posted Write 2nd 3rd 4th 5th 6th Prefetchable Memory Base and Limit Registers 2nd 3rd Primary Latency Timer Register Processor VID/FID Producer/Consumer Model 2nd 3rd Programmed I/O 2nd Programmed I/O Transactions Protocol Errors 2nd 3rd 4th Pseudo-Synchronous Clock Mode Pseudo-Synchronous Clocking Mode PWROK 2nd 3rd 4th 5th 6th 7th 8th 9th
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