HyperTransportв„ў System Architecture
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Scalability 2nd 3rd Scalable Bandwidth Scalable Clock Speed Scalable Data Width Secondary Bus Non-Prefetchable Window Base Secondary Bus Non-Prefetchable Window Control Register Secondary Bus Prefetchable Window Control Register Secondary Bus Window Base register Secondary Status Register 2nd Sequence ID 2nd 3rd 4th 5th Signal Groups Signaling Interrupt Acknowledge Signaling INTR Sized Byte Read 2nd 3rd Sized Byte Write 2nd Sized Dword Read 2nd 3rd Sized Read 2nd Sized Read Transactions Sized Write Sized Write Transactions Slave Host Bridge 2nd Slave/Primary Interface 2nd SM Request Packet Format, Downstream SM Request, Sources of Source Tag 2nd 3rd Special Cycles 2nd Specification 1.04 Status Register 2nd 3rd 4th 5th Stop Clock Signal STOP_GRANT Cycles Storage Semantics 2nd STPCLK# STPCLK# Signaling Strongly Ordered Sequence Subtractive Decode 2nd 3rd Sync Flood 2nd 3rd 4th Sync Pattern Sync/Error Packet Synchronous Clock Mode System Management 2nd 3rd System Management Address Range System Management Commands, Upstream System Management Mode 2nd
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