HP ProLiant Servers AIS: Official Study Guide and Desk Reference

What is bus width?

1. The number of bus cycles that occur per second

2. The number of electrical lines in a bus

3. The process used to transfer data

4. The amount of data that can flow across a bus during a period of time

Answer: B

Over what system bus are control signals usually sent?

Answer: Control bus

What is the formula for maximum transfer rate of a bus?

1. (Speed x Width)/Clock cycles per transfer

2. (Speed x Clock cycles per bus cycle)/Width

3. (Width x Clock cycles per bus cycle)/Speed

4. Speed/(Clock cycles per bus cycle x Width)

Answer: A

What are four fundamental adjustments that can improve system performance?

Answer: Any four of the following are acceptable answers:

1. Increase the speed at which bus cycles take place. This usually means increasing the clock speed of the processor.

2. Increase the speed at which devices, especially system memory, can communicate with the processor. This involves implementing high-speed memory or adding a cache.

3. Increase the width of the data bus to increase the amount of information passed in a single bus cycle.

4. Implement modified bus cycles, such as a burst cycle.

5. Add concurrent processes, such as dual independent buses or multiprocessing.

What is a bus master device?

Answer: A device connected to the bus that communicates directly with other devices on the bus without going through the processor.

How many expansion slots operating at 66MHz can a PCI-X bus segment support?

Answer: Four or more.

How long does PCI-X allow for the decode logic to occur?

Answer: 7ns

Match the following terms and descriptions:

Answer:

PCI Express: Defines a packetized protocol and a load/store architecture

PCI-X 2.0: Incorporates error checking and correcting

USB: Enables you to hot plug peripheral devices without restarting or reconfiguring the system