| 1: | What is bus width? The number of bus cycles that occur per second The number of electrical lines in a bus The process used to transfer data The amount of data that can flow across a bus during a period of time
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| 2: | Over what system bus are control signals usually sent? |
| 3: | What is the formula for maximum transfer rate of a bus? (Speed x Width)/Clock cycles per transfer (Speed x Clock cycles per bus cycle)/Width (Width x Clock cycles per bus cycle)/Speed Speed/(Clock cycles per bus cycle x Width)
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| 4: | What are four fundamental adjustments that can improve system performance? |
| 5: | What is a bus master device? |
| 6: | How many expansion slots operating at 66MHz can a PCI-X bus segment support? |
| 7: | How long does PCI-X allow for the decode logic to occur? |
| 8: | Match the following terms and descriptions: PCI Express | Incorporates error checking and correcting | PCI-X 2.0 | Defines a packetized protocol and a load/store architecture | USB | Enables you to hot plug peripheral devices without restarting or reconfiguring the system |
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