From ASICs to SOCs: A Practical Approach

In order to bring down the cost of systems, vendors convert their FPGA designs into ASICs. In some cases, multiple FPGAs are integrated into a single ASIC. Some ASIC vendors match the exact package and pinout of the original FPGA designs.

The market targeted for these migrations is the middle ground of the ASIC market. ASIC variations that are offered include gate array/embedded array and standard- cell technologies, multimetal-layer processing, high-speed operation, low-power and low-voltage operation.

Figure 2.6 shows a typical conversion flow from FPGA to ASIC. The FPGA netlist typically comes in the form of Verilog, EDIF, VHDL, or XNF.

Design analysis usually consists of boundary scan, power analysis, design-rule checks, pin-pad selection, and package finalization .

Depending on the complexity of the design and its test vectors, the conversion flow changes slightly. ASIC design houses usually have defined flows for both synchronous and asynchronous designs with full or partial test vectors.

In addition to cost reduction, other benefits of the conversion include the following:

• Die size reduction

• Power consumption reduction

• Enhanced performance

• Reliable high-volume production capacity

• Low NRE

The following tips should be considered for the FPGA to ASIC migration:

• Some features, such as RAM initialization and configuration logic, are expensive to implement in an ASIC. These features should be avoided in ASICs.

• Use synchronous design methodology.

• Leave extra power and ground pins for your pinout.

• Use one external clock and external reset.

• Use standards as much as possible.