From ASICs to SOCs: A Practical Approach

For a successful tape out, you should complete the following steps:

• Functional sign-off

• Timing sign-off

• DFT sign-off

• Physical sign-off

Some tips and guidelines for physical design were discussed in Section 4.3 including the following:

• After generating a floorplan with a chip-level timing budget, the logical hierarchy should match the physical one.

• For hierarchical methodology, use multiple placement-and-routing stages.

Examples of optimization techniques are gate sizing, buffer insertion/deletion, and placement optimization.

Two examples of new physical design techniques were presented in Section 4.4.