An Introduction to Ultra Wideband Communication Systems

5.2. Modulators

Modulation in the conventional sense of modifying some characteristic of a carrier wave is not employed in I-UWB transmitters. There is no carrier wave, but the characteristic of the pulses must be modified in some manner. The pulses must have some unique property in order to attach information. In carrier-based systems, there is usually some circuit that specifically performs the modulation. Pulse generator circuits in I-UWB transmitters perform a direct data bits to RF conversion so the modulation is often done by bit timing.

The simplest modulation is amplitude modulation or on/off keying (OOK). The pulser is turned on and off to represent data bits. While very simple, an OOK system is at a significant power disadvantage because, assuming equal number of ones and zeros, the transmitter is off half the time. More advantageous are pulse position modulation, (PPM), biphase pulse polarity modulation (antipodal PAM), and pulse width modulation (PWM). The Aether Wire transmitter previously described uses a type of antipodal PAM [15].

PPM can be accomplished with bit timing; both analog and digital modulation is possible. Avalanche transistor, SRD, and other pulser circuits simply put fast edges on pulses coming from a baseband signal processor. Analog PPM was used in early analog I-UWB systems.

Digital control of the time delay between pulses is possible. A dedicated timing IC is available [18]. Figure 5.24 is a simplified block diagram of the timing device. The VCO controlled by a phase-locked loop (PLL) runs at approximately 2.5 GHz with a 10 MHz reference. Each cycle of the 2.5 GHz VCO advances the 8-bit synchronous counter one count. Each count represents a 390 picosecond time advance. The value loaded into the comparator determines the number of 390 picosecond steps that can occur before the output of a course delay pulse. The value loaded into the comparator can be changed dynamically so that the interval between output pulses can be controlled.

The fine delay generator is an analog circuit based on an I/Q vector modulator. Figure 5.25 is a block diagram of the fine delay generator. The fine delay generator is a voltage controlled phase shifter. The values for sin(a) and cos(a) are generated by an 8-bit digital to analog converter (DAC). With the 8-bit DAC it is possible to divide the 390 picosecond coarse delay pulse into 1.52 picosecond increments. The value in the comparator and the DAC are controlled by a baseband processor.

The output pulse from the timer is used to drive an SRD or other fast-rise time pulser. An improved version of this device is described in [19].

Digital PWM can be accomplished by combining a pair of pulsers. Two SRD pulsers of the type shown in Figure 5.8 with different pulse widths can be combined through a RF power combiner, and the SRD with the desired pulse width can be triggered at the desired time.