Upgrading and Repairing Servers

Standard DRAM was used in early servers up through about 1996. This memory is accessed through a technique called paging. Normal memory access requires that a row-and-column address be selected, which takes time. Paging enables faster access to all the data within a given row of memory by keeping the row address the same and changing only the column. If a memory address is needed from a range of memory outside the current page, wait states are added to the memory access cycle.

Fast Page Mode DRAM

Early servers took advantage of a feature called burst mode to speed up access to adjacent memory locations. A typical burst mode access of standard DRAM is expressed as x-y-y-y, where x is the time for the first access (latency plus cycle time), and y represents the number of cycles required for each consecutive access. Standard 60ns DRAM normally runs 5-3-3-3 burst mode timing. This means the first access takes a total of five cycles (on a 66MHz system bus, this is about 75ns total or 5x15ns cycles), and the consecutive cycles take three cycles each (3x15ns = 45ns). As you can see, the actual system timing is somewhat less than the memory is technically rated for. Without the bursting technique, memory access would be 5-5-5-5 because the full latency would be necessary for each memory transfer.

Memory that uses paging and burst mode is referred to as Fast Page Mode (FPM) DRAM. FPM DRAM was the leading type of memory used in Pentium and Pentium Pro-class systems until 1995.

EDO DRAM

In 1995, a newer type of memory called extended data out (EDO) DRAM became available for Pentium and newer servers. EDO, a modified form of FPM memory patented by Micron Technologies, is sometimes referred to as Hyper Page mode. EDO memory consists of specially manufactured chips that allow a timing overlap between successive accesses. The name extended data out refers specifically to the fact that unlike with FPM, the data output drivers on the chip are not turned off when the memory controller removes the column address to begin the next cycle. This enables the next cycle to overlap the previous one, saving approximately 10ns per cycle and providing a real-world performance boost of about 5% over FPM DRAM.

Intel server-class chipsets built in the 19951998 period that support EDO include the 430HX (Triton II), 440FX (Natoma), 440LX, and 450NX (originally known as the 440NX). After this time, Intel servers began to use RDRAM or other, newer memory technologies.

SDRAM

SDRAM, short for synchronous DRAM, is a type of DRAM that runs in synchronization with the memory bus. SDRAM delivers information in very high-speed bursts, using a high-speed, clocked interface. SDRAM removes most of the latency involved in asynchronous DRAM because the signals are already in synchronization with the motherboard clock.

As with EDO RAM, chipset must support SDRAM memory for it to be usable in your system. The first Intel server-class chipset to support SDRAM was the 440LX, which also supported EDO DRAM. Other Intel Pentium II/III/Xeon-class chipsets to support SDRAM included the 440BX and 440GX. SDRAM support has also been a popular choice for many third-party chipsets. See Chapter 3, "Server Chipsets," for details.

SDRAM performance is dramatically improved over that of FPM or EDO RAM. Because SDRAM is still a type of DRAM, the initial latency is the same, but overall cycle times are much faster than with FPM or EDO. SDRAM timing for a burst access would be 5-1-1-1, meaning that four memory reads would complete in only 8 system bus cycles, compared to 11 cycles for EDO and 14 cycles for FPM. This makes SDRAM almost 20% faster than EDO. Besides being capable of working in fewer cycles, SDRAM is also capable of supporting up to 133MHz (7.5ns) system bus cycling.

SDRAM is sold in dual inline memory module (DIMM) form and is often rated by megahertz speed rather than by nanosecond cycling time, which was confusing during the change from FPM and EDO DRAM.

To meet the stringent timing demands of its chipsets, Intel created specifications for SDRAM called PC66, PC100, and PC133. To meet the PC100 specification, 8ns chips are usually required. Normally, you would think 10ns would be considered the proper rating for 100MHz operation, but the PC100 specification calls for faster memory to ensure that all timing parameters are met.

In May 1999, the Joint Electron Device Engineering Council (JEDEC) created a specification called PC133. JEDEC achieved this 33MHz speed increase by starting with the PC100 specification and tightening up the timing and capacitance parameters. The faster PC133 quickly caught on as the most popular version of SDRAM for any systems running a 133MHz processor bus. The original chips used in PC133 modules were rated for exactly 7.5ns, or 133MHz; later ones were rated at 7.0ns, or 143MHz. These faster chips were still used on PC133 modules, but they allowed for improvements in column address strobe latency (abbreviated as CAS or CL), which somewhat improves overall memory cycling time.

Table 5.5 shows the timing, rated chip speeds, and standard module speeds for various SDRAM DIMMs.

Table 5.6 shows the standard SDRAM module types and resulting bandwidths.

^[1] Key: MT/s = megatransfers per second; MBps = megabytes per second; ns = nanoseconds (billionths of a second); DIMM = dual inline memory module; and SDR = single data rate.

Caution

At one time, PC133 memory was backward compatible with PC100 memory. However, current PC133 memory uses different sizes of memory chips than those used by PC100 modules. If you use servers that require PC100 memory, you should not attempt to use PC133 memory in them unless the memory is specifically identified by the vendor as being compatible with your system. You can use the online memory configurators provided by most major memory vendors to ensure that you get the right memory for your server.