Upgrading and Repairing PCs (17th Edition)

The heart of any motherboard is the various buses that carry signals between the components. A bus is a common pathway across which data can travel within a computer. This pathway is used for communication and can be established between two or more computer elements.

The PC has a hierarchy of different buses. Most modern PCs have at least three buses; some have four or more. They are hierarchical because each slower bus is connected to the faster one above it. Each device in the system is connected to one of the buses, and some devices (primarily the chipset) act as bridges between the various buses.

The main buses in a modern system are as follows:

• Processor bus. Also called the front-side bus (FSB), this is the highest-speed bus in the system and is at the core of the chipset and motherboard. This bus is used primarily by the processor to pass information to and from cache or main memory and the North Bridge of the chipset. The processor bus in a modern system runs at 66MHz, 100MHz, 133MHz, 200MHz, 266MHz, 400MHz, 533MHz, 800MHz, or 1066MHz and is normally 64 bits (8 bytes) wide.

• AGP bus. This is a 32-bit bus designed specifically for a video card. It runs at 66MHz (AGP 1x), 133MHz (AGP 2x), 266MHz (AGP 4x), or 533MHz (AGP 8x), which allows for a bandwidth of up to 2133MBps. It is connected to the North Bridge or Memory Controller Hub of the chipset and is manifested as a single AGP slot in systems that support it. Newer systems are phasing out AGP slots in favor of PCI-Express.

• PCI-Express. The PCI-Express bus is a third-generation development of the PCI bus. PCI-Express is a differential signaling bus that can be generated by either the North Bridge or South Bridge. The speed of PCI-Express is described in terms of lanes. Each bidirectional dual-simplex lane provides a 2.5Gbps transfer rate in each direction (2Gbps effective speed). Thus a single-lane PCI-Express slot (known as x1) runs at 2.5Gbps in each direction. Some systems support PCI-Express x4, which provides 10Gbps in each direction. PCI-Express video cards generally use the x16 slot, which provides 40Gbps in each direction.

• PCI-X. PCI-X is a second-generation development of the PCI bus that provides faster speeds than PCI but is backward-compatible with PCI. It is used primarily in workstation and server installations. PCI-X supports 64-bit slots that are backward-compatible with 64-bit and 32-bit PCI cards. PCI-X version 1 runs at 133MHz, whereas PCI-X 2.0 supports operation at up to 533MHz. Typically, PCI-X 2.0's bandwidth is subdivided among multiple PCI-X and PCI slots. Although a few South Bridge chips can generate the PCI-X bus, most chipsets that support PCI-X use a separate PCI-X bus chip.

• PCI bus. This is usually a 33MHz 32-bit bus found in virtually all systems since the days of the Intel 486 CPU. Some newer systems include an optional 66MHz 64-bit versionmostly workstations or server-class systems. This bus is generated by either the chipset North Bridge in North/South Bridge chipsets or the I/O Controller Hub in chipsets using hub architecture. This bus is manifested in the system as a collection of 32-bit slots, normally white in color and numbering from four to six on most motherboards. High-speed peripherals, such as SCSI adapters, network cards, video cards, and more, can be plugged into PCI bus slots. PCI-X and PCI-Express are faster developments of the PCI bus. PCI-Express motherboards and systems began to appear in mid-2004.

• ISA bus. This is an 8MHz 16-bit bus that has disappeared from recent systems after first appearing in the original PC in 8-bit, 5MHz form and in the 1984 IBM AT in full 16-bit 8MHz form. It is a very slow-speed bus, but it was ideal for certain slow-speed or older peripherals. It has been used in the past for plug-in modems, sound cards, and various other low-speed peripherals. The ISA bus is created by the South Bridge part of the motherboard chipset, which acts as the ISA bus controller and the interface between the ISA bus and the faster PCI bus above it. The Super I/O chip usually was connected to the ISA bus on systems that included ISA slots.

Some motherboards feature a special connector called an Audio Modem Riser (AMR) or a Communications and Networking Riser (CNR). These are dedicated connectors for cards that are specific to the motherboard design to offer communications and networking options. They are not designed to be general-purpose bus interfaces, and few cards for these connectors are offered on the open market. Usually, they're offered only as an option with a given motherboard. They are designed such that a motherboard manufacturer can easily offer its boards in versions with and without communications options, without having to reserve space on the board for optional chips. Normal network and modem options offered publicly, for the most part, will still be PCI based because the AMR/CNR connection is somewhat motherboard specific. Figure 4.59 compares these connectors, and Figure 4.60 compares typical AMR and CNR riser cards. Note that the newest motherboards have largely abandoned AMR and CNR slots.

Several hidden buses exist on modern motherboardsbuses that don't manifest themselves in visible slots or connectors. I'm talking about buses designed to interface chipset components, such as the Hub Interface and the LPC bus. The Hub Interface is a quad-clocked (4x) 66MHz 8-bit bus that carries data between the MCH and ICH in hub architecture chipsets made by Intel. It operates at a bandwidth of 266MBps and was designed as a chipset component connection that is faster than PCI and yet uses fewer signals for a lower-cost design. Some recent workstation/server chipsets and the latest 9xx-series desktop computer chipsets from Intel use faster versions of the hub interface. The most recent chipsets from major third-party vendors also bypass the PCI bus with direct high-speed connections between chipset components.

In a similar fashion, the LPC bus is a 4-bit bus that has a maximum bandwidth of 16.67MBps; it was designed as an economical onboard replacement for the ISA bus. In systems that use LPC, it typically is used to connect Super I/O chip or motherboard ROM BIOS components to the main chipset. LPC is faster than ISA and yet uses far fewer pins and enables ISA to be eliminated from the board entirely.

The system chipset is the conductor that controls the orchestra of system components, enabling each to have its turn on its respective buses. Table 4.74 shows the widths, speeds, data cycles, and overall bandwidth of virtually all PC buses.

Note that many of the buses use multiple data cycles (transfers) per clock cycle to achieve greater performance. Therefore, the data transfer rate is higher than it would seem for a given clock rate, which allows for an easy way to take an existing bus and make it go faster in a backward-compatible way.

The following sections discuss the processor and other subset buses in the system and the main I/O buses mentioned in the previous table.

The Processor Bus (Front-Side Bus)

The processor bus (also called the front-side bus or FSB) is the communication pathway between the CPU and motherboard chipset, more specifically the North Bridge or Memory Controller Hub. This bus runs at the full motherboard speedtypically between 66MHz and 800MHz in modern systems, depending on the particular board and chipset design. This same bus also transfers data between the CPU and an external (L2) memory cache on Socket-7 (Pentium class) systems. Figure 4.61 shows how this bus fits into a typical Socket 7 PC system.

Figure 4.61 also shows where and how the other main buses, such as the PCI and ISA buses, fit into the system. As you can see, there is clearly a three-tier architecture with the fastest CPU bus on top, the PCI bus next, and the ISA bus at the bottom. Various components in the system are connected to one of these three main buses.

Socket 7 systems have an external (L2) cache for the CPU; the L2 cache is mounted on the motherboard and connected to the main processor bus that runs at the motherboard speed (usually between 66MHz and 100MHz). Thus, as the Socket 7 processors became available in faster and faster versions (through increasing the clock multiplier in the chip), the L2 cache unfortunately remained stuck on the motherboard running at the relatively slow (by comparison) motherboard speed. For example, the fastest Intel Socket 7 systems ran the CPU at 233MHz, which was 3.5x the CPU bus speed of 66MHz. Therefore, the L2 cache ran at only 66MHz. The fastest Socket 7 systems used the AMD K6-2 550 processor, which ran at 550MHz5.5x a CPU bus speed of 100MHz. In those systems, the L2 cache ran at only 100MHz.

The problem of the slow L2 cache was first solved in the P6 class processors, such as the Pentium Pro, Pentium II, Celeron, Pentium III, and AMD Athlon and Duron. These processors used either Socket 8, Slot 1, Slot 2, Slot A, Socket A, or Socket 370. They moved the L2 cache off the motherboard and directly onto the CPU and connected it to the CPU via an on-chip back-side bus. Because the L2 cache bus was called the back-side bus, some in the industry began calling the main CPU bus the front-side bus. I still usually refer to it simply as the CPU bus.

By incorporating the L2 cache into the CPU, it can run at speeds up to the same speed as the processor itself. Most processors now incorporate the L2 cache directly on the CPU die, so the L2 cache runs at the same speed as the rest of the CPU. Others (mostly older versions) used separate die for the cache integrated into the CPU package, which ran the L2 cache at some lower multiple (one-half, two-fifth, or one-third) of the main CPU. Even if the L2 ran at half or one-third of the processor speed, it still was significantly faster than the motherboard-bound cache on the Socket 7 systems.

In a Slot-1 type system the L2 cache is built in to the CPU but running at only half the processor speed. Slot A systems run the cache at one-half or one-third speed. The CPU bus speed increased from 66MHz (used primarily in Socket 7 systems) to 100MHz, enabling a bandwidth of 800MBps. Note that most of these systems included AGP support. Basic AGP was 66MHz (twice the speed of PCI), but most of these systems incorporated AGP 2x, which operated at twice the speed of standard AGP and enabled a bandwidth of 533MBps. These systems also typically used PC-100 SDRAM DIMMs, which have a bandwidth of 800MBps, matching the processor bus bandwidth for the best performance.

Slot 1 was dropped in favor of Socket 370 for the Pentium III and Celeron systems. This was mainly because these newer processors incorporated the L2 cache directly into the CPU die (running at the full-core speed of the processor) and an expensive cartridge with multiple chips was no longer necessary. At the same time, processor bus speeds increased to 133MHz, which enabled a throughput of 1066MBps. Figure 4.62 shows a typical Socket 370 system design. AGP speed was also increased to AGP 4x, with a bandwidth of 1066MBps.

Note the use of what Intel calls "hub architecture" instead of the older North/South Bridge design. This moves the main connection between the chipset components to a separate 266MBps hub interface (which has twice the throughput of PCI) and enables PCI devices to use the full bandwidth of PCI without fighting for bandwidth with a South Bridge. Also note that the flash ROM BIOS chip is now referred to as a Firmware Hub and is connected to the system via the LPC bus instead of via the Super I/O chip as in older North/South Bridge designs. The ISA bus is no longer used in most of these systems, and the Super I/O is connected via the LPC bus instead of ISA. The Super I/O chip also can easily be eliminated in these designs. This is commonly referred to as a legacy-free system because the ports supplied by the Super I/O chip are now known as legacy ports. Devices that would have used legacy ports must then be connected to the system via USB instead, and such systems would feature two USB controllers, with up to four total ports (more can be added by attaching USB hubs).

AMD processor systems adopted a Socket A design, which is similar to Socket 370 except it uses faster processor and memory buses. Although early versions retained the older North/South Bridge design, more recent versions use a design similar to Intel's hub architecture. Note the high-speed CPU bus running up to 333MHz (2667MBps throughput) and the use of DDR SDRAM DIMM modules that support a matching bandwidth of 2667MBps. It is always best for performance when the bandwidth of memory matches that of the processor. Finally, note how most of the South Bridge components include functions otherwise found in Super I/O chips; when these functions are included the chip is called a Super South Bridge.

The Pentium 4 uses a Socket 423 or Socket 478 design with hub architecture (see Figure 4.63). This design is most notable for including a 400MHz, 533MHz, or 800MHz CPU bus with a bandwidth of 3200MBps, 4266MBps, or 6400MBps. The 533MHz and 800MHz models are currently faster than anything else on the market. In this example, note the use of dual-channel PC3200 (DDR400) SDRAM. A single PC-3200 DIMM has a bandwidth of 3200MBps, but when running dual-channel (identical pairs of memory) mode, it has a bandwidth of 6400MBpswhich matches the bandwidth of the 800MHz CPU bus models of the Pentium 4 for best performance. Processors with the 533MHz CPU bus can use pairs of PC2100 (DDR266) or PC2700 (DDR333) memory modules in dual channel mode to match the 4266MBps throughput of this memory bus. It is always best when the throughput of the memory bus matches that of the processor bus.

The Athlon 64 uses the high-speed HyperTransport architecture to connect the North Bridge or AGP Graphics Tunnel chip to the processor (Socket 754, 939, or 940). Most Athlon 64 chipsets use the 16-bit/800MHz version, but the latest chipsets designed for the new Socket 939 Athlon 64 FX-53 use the faster 16-bit/1GHz version to support faster DDR-2 memory.

However, the Athlon 64's most significant departure from conventional computer architecture is the location of the memory controller. Rather than being located in the North Bridge/MCH/GMCH chip, the Athlon 64/FX/Opteron architecture places the memory controller in the processor itself. This eliminates slow-downs caused by the use of an external memory controller and helps boost performance.

One drawback to the design, however, is that new memory technologies, such as DDR-2, require that the processor itself be redesigned.

Figure 4.64 illustrates an Athlon 64 FX-53based system that uses the new PCI-Express x1 and PCI-Express x16 expansion slot designs.

Because the purpose of the processor bus is to get information to and from the CPU at the fastest possible speed, this bus typically operates at a rate faster than any other bus in the system. The bus consists of electrical circuits for data, addresses (the address bus, which is discussed in the following section), and control purposes. Most processors since the original Pentium have a 64-bit data bus, so they transfer 64 bits (8 bytes) at a time over the CPU bus.

The processor bus operates at the same base clock rate as the CPU does externally. This can be misleading because most CPUs these days run at a higher clock rate internally than they do externally. For example, an AMD Athlon 64 3800+ system has a processor running at 2.4GHz internally but only 400MHz externally, whereas a Pentium 4 3.4GHz runs at 3.4GHz internally but only 800MHz externally. In newer systems, the actual processor speed is some multiple (2x, 2.5x, 3x, and higher) of the processor bus.

The processor bus is tied to the external processor pin connections and can transfer 1 bit of data per data line every cycle. Most modern processors transfer 64 bits (8 bytes) of data at a time.

To determine the transfer rate for the processor bus, you multiply the data width (64 bits or 8 bytes for a Celeron/Pentium III/4 or Athlon/Duron/Athlon XP/Athlon 64) by the clock speed of the bus (the same as the base or unmultiplied clock speed of the CPU).

For example, if you are using a Pentium 4 3.6GHz processor that runs on an 800MHz processor bus, you have a maximum instantaneous transfer rate of roughly 6400MBps. You get this result by using the following formula:

800MHz x 8 bytes (64 bits) = 6400MBps

With slower versions of the Pentium 4, you get either

533.33MHz x 8 bytes (64 bits) = 4266MBps

or

400MHz x 8 bytes (64 bits) = 3200MBps

With Socket A (Athlon XP), you get

333.33MHz x 8 bytes (64 bits) = 2667MBps

or

266.66MHz x 8 bytes (64 bits) = 2133MBps

or

200MHz x 8 bytes (64 bits) = 1600MBps

With Socket 370 (Pentium III), you get

133.33MHz x 8 bytes (64 bits) = 1066MBps

or

100MHz x 8 bytes (64 bits) = 800MBps

This transfer rate, often called the bandwidth of the processor bus, represents the maximum speed at which data can move. Refer to Table 4.72 for a more complete list of various processor bus bandwidths.

The Memory Bus

The memory bus is used to transfer information between the CPU and main memorythe RAM in your system. This bus is usually connected to the motherboard chipset North Bridge or Memory Controller Hub chip. Depending on the type of memory your chipset (and therefore motherboard) is designed to handle, the North Bridge runs the memory bus at various speeds. The best solution is if the memory bus runs at the same speed as the processor bus. Systems that use PC133 SDRAM have a memory bandwidth of 1066MBps, which is the same as the 133MHz CPU bus. In another example, Athlon systems running a 266MHz processor bus also run PC2100 DDR-SDRAM, which has a bandwidth of 2133MBpsexactly the same as the processor bus in those systems. Systems running a Pentium 4 with its 400MHz processor bus also use dual-channel RDRAM memory, which runs 1600MBps for each channel, or a combined bandwidth (both memory channels run simultaneously) of 3200MBps, which is exactly the same as the Pentium 4 CPU bus. Pentium 4 systems with the 533MHz bus run dual-channel DDR PC2100 or PC2700 modules, which match or exceed the throughput of the 4266MBps processor bus.

Running memory at the same speed as the processor bus negates the need for having cache memory on the motherboard. That is why when the L2 cache moved into the processor, nobody added an L3 cache to the motherboard. Some very high-end processors, such as the Itanium and Itanium 2 and the Intel Pentium 4 Extreme Edition, have integrated 2MB4MB of full-core speed L3 cache into the CPU. However, the most recent high-performance chips, such as the new Pentium Extreme Edition, use only L1 and L2 cache. Thus, it appears that L2 cache will continue to be the most common type of secondary cache for the foreseeable future.

Note

Notice that the main memory bus must transfer data in the same width as the processor bus. This defines the size of what is called a bank of memory, at least when dealing with anything but RDRAM. Memory banks and their widths relative to processor buses are discussed in the section "Memory Banks" in Chapter 6.

The Need for Expansion Slots

The I/O bus or expansion slots enable your CPU to communicate with peripheral devices. The bus and its associated expansion slots are needed because basic systems can't possibly satisfy all the needs of all the people who buy them. The I/O bus enables you to add devices to your computer to expand its capabilities. The most basic computer components, such as sound cards and video cards, can be plugged into expansion slots; you also can plug in more specialized devices, such as network interface cards, SCSI host adapters, and others.

Note

In most modern PC systems, a variety of basic peripheral devices are built in to the motherboard. Most systems today have at least dual (primary and secondary) IDE interfaces, four USB ports, a floppy controller, two serial ports, a parallel port, keyboard, and mouse controller built directly into the motherboard. These devices are usually distributed between the motherboard chipset South Bridge and the Super I/O chip. (Super I/O chips are discussed earlier in this chapter.)

Many add even more items, such as a built-in sound card, video adapter, SCSI host adapter, network interface or IEEE 1394a port, that also are built in to the motherboard. Those items, however, might not be built in to the motherboard chipset or Super I/O chip; they are sometimes configured as additional chips installed on the board. Nevertheless, these built-in controllers and ports still use the I/O bus to communicate with the CPU. In essence, even though they are built in, they act as if they were cards plugged into the system's bus slots, including using system resources in the same manner.