Pcb Noise and Interference

Article first published in EDN Magazine , January 18, 2001

Terminations exist to control ringing. Ringing (sometimes called overshoot or resonance ) is the tendency for signals within a distributed transmission environment to slosh back and forth, bouncing from end to end and creating oscillatory ripples in the received digital data.

The best ways to control ringing on very long transmission lines are source termination, end termination, and both-ends termination. The both-ends termination is supremely tolerant of imperfections within the transmission system and within the terminators themselves .

Figure 5.14 depicts a time-space analysis of the both-ends termination. The graph depicts the evolution of one step edge from the time the driver injects it into the transmission line until it dissipates, bouncing back and forth.

Figure 5.14. Reflection coefficients govern how each step edge bounces back and forth throughout a transmission line.

The horizontal axis represents various physical positions along the transmission line from the source position (at the far left) to the load (at the right). The vertical dimension represents the flow of time, beginning at time t , when the driver first impresses onto the line a rising step edge of amplitude A .

As the step edge interacts with various obstacles along the way, each encounter spawns a new reflected signal. The time-space diagram tracks the magnitude of all the reflection products. Each arrow is labeled according to the attenuation factors (reflection coefficients) it encounters. The four reflection coefficients G 1 to G 4 are schematically defined at the top of the figure. Assume for this simple example that all four coefficients G 1 to G 4 are small, meaning that the line is well-terminated at both ends ( G 1 << 1 and G 4 << 1) and that the obstacle in the middle, whatever it is, generates only mild reflections ( G 2 << 1 and G 3 << 1).

In general, the amplitude of any step passing through obstacle n is multiplied by a factor (1 + G n ). For simplicity, the figure leaves out these (1 + G n ) terms under the assumption that, in this discussion, G n is always small, so (1 + G n ) must be reasonably close to 1.

The first thing you should notice about the diagram is that all the first-order products (solid arrows), having bounced one time, are heading from right to left. None of these products reach the endpoint. Only second-order products (dashed arrows) and higher order even-numbered products can reach the endpoint. Because each reflection attenuates the signal, the higher order products are very small. In Figure 5.14 the higher-order products appear with successively faint lines, denoting that they are too small to worry about.

The next thing to notice is that each of the second-order products has been attenuated by two small coefficients. For example, both G 4 and G 3 attenuate the product arriving at time t 2 . Both G 2 and G 1 attenuate the product arriving at time t 3 . In both cases, the surviving signal has been double-attenuated. That's the beauty of a double-end-terminated net. All second-order reflection products are attenuated twice. It hardly matters what kind of obstacle lies in the middle; the terminators always get a chance to damp out the second-order-reflected products.

Contrast that behavior with what would happen on a plain end-terminated line. In that case, the magnitude of the coefficient G 1 would equal almost unity. (A powerful, low-impedance driver creates a reflection coefficient at the source of approximately 1.) The second-order term at time t 3 would then loom much larger.

The both-ends termination attenuates all second-order reflection products.

Similarly, on a plain source-terminated line, the reflection coefficient G 4 would be practically +1, enlarging the second-order term at time t 2 .

The both-ends termination attenuates all second-order reflection products, improving signal quality over any single termination. Mathematically, reducing the magnitude of both G 4 and G 1 renders your design impervious to variations in G 2 and G 3 .

Of course, the big disadvantage of the both-ends termination is the half-amplitude received signal. The driver (whose source impedance matches the characteristic impedance of the transmission line) produces only a half-sized step. This half-sized step remains half-sized at the end-terminated endpoint. It takes an especially sensitive receiver to work with a both-ends-terminated transmission line.

The both-ends termination is an excellent choice for very high-speed serial links in which you anticipate encountering connectors, vias, or other impedance discontinuities in the middle of the line and for which you can afford a super-sensitive receiver.

where

a is the peak magnitude of the reflected signal, volts ,

D V is the amplitude of the incoming step, volts,

t is a time constant computed from the lumped-element capacitance C L and the transmission-line impedance Z C , having the value t = Z C C L /2,

and

t r is the 10% to 90% risetime of the incoming step, in seconds.

where

t is a time constant computed from the lumped-element capacitance C and the transmission-line impedance Z C , having a value t = Z C C L /2, and

t r is the 10% to 90% risetime of the incoming step, in seconds.

Article first published in EDN Magazine , November 11, 1999

Driving home from the Spokane, Washington, airport one clear night, a steaming cup of coffee cradled in my hand, I took a shortcut across the Colville Indian Reservation. Almost immediatelybam!my truck hit a giant pothole. Hot java flew in every direction. I stopped the truck to see what I'd hit.

The pothole was about a foot across. It was filled with water, so it was difficult to see. It looked like it would be a hazard to other motorists, so I scrounged around for a big rock and dropped it into the hole.

The rock wasn't a perfect fit. It bulged in the center, but it seemed to be the right overall size for the hole. I backed up and tried driving over the hole again (no coffee this time). It was much better. Satisfied with my good deed, I continued the drive homeward.

This incident reminded me of a similar treatment used in transmission-line design. You can improve a big imperfection in a transmission line (such as a capacitive load) by adding a compensating imperfection to the line. One imperfection partially cancels the other. Going back to the driving analogy, as long as the residual imperfection is smaller than your wheels, you won't feel it.

Adjustments to transmission-line width can partially compensate for one isolated capacitive load.

Figure 5.16 illustrates the scenario. Adjustments to the transmission-line width on either side of the load partially compensate for the capacitive load. The load adds extra capacitance to the line, but the extra-skinny trace takes away a compensating amount of capacitance (and adds some inductance). The negative reflection from the capacitive lump is counteracted by a positive reflection from the skinny trace segment.

Figure 5.16. A short section of a skinny pc-board trace partially compensates for a lumped capacitive load.

The skinny-line adjustment in the figure can substantially reduce the reflected wave height of any incoming edge whose rise or fall time is slower than the effective delay of the adjusted segment.

Given a fixed value of k = Z 1 /Z corresponding to the skinniest transmission line (highest Z 1 ) you can reliably produce, select the length of the adjusted segment ( x ) so that the ratio of overall inductance and capacitance in the adjusted segment, including the effect of the lumped load, produces an effective impedance of Z . You mathematically represent this impedance condition as

Equation 5.17

Solving for the adjusted trace length x tells you how long (in meters ) to make the skinny segment for a best compensating match. You may notice in this next formula that the skinnier you make the adjusted trace (the higher the Z 1 and thus the greater the k ), the shorter you can make the adjusted segment:

Equation 5.18

The skinny-trace compensation technique works only when the rise or fall time of the incoming edge is significantly slower (three to six times slower) than the effective delay of the adjusted structure. The effective delay t LOADED of the adjusted structure (including load) is

Equation 5.19

Equation [5.19] assumes you have implemented the trace length prescribed by [5.18]. Equation [5.19] tells you whether the pothole-filling technique will be effective. Namely, when the time-constant Z C L is much less than the signal rise time, it's easy to find a reasonable value of k for which t LOADED remains acceptably small.

Example of pothole calculation

The resulting structure remains practically invisible to any signal with a rise or fall time slower than 600 psec.

On the other hand, if Z C L is comparable with or larger than the signal rise or fall time, you won't be able to adequately compensate for such a large C L . To fix that problem, you need a smaller C L , a smaller Z , or a slower rise and fall time.

In the automotive world, a similar effect applies: Potholes bigger than your wheels are not easily filled with a single rock.

where

Z is the impedance of the surrounding transmission medium, W ,

v is the unloaded trace velocity of the adjusted segment, m/s,

k = Z 1 / Z defines the unloaded impedance of the adjusted segment,

( x / v )( Z k ) is the unloaded inductance of the adjusted segment, H,

( x / v )/( Z k ) is the total capacitance of the adjusted segment, F, and

L S represents the series inductance, H.

Article first published in EDN Magazine , May 11, 2000

Right-angle bends in pc-board traces perform perfectly well in digital designs in speeds as fast as 2 Gbps.

In most digital designs, the right-angle bend is electrically smaller than a rising edge. For example, the delay through a right-angle bend in an 8-mil wide, 50- W microstrip trace in FR-4 is on the order of 1 psec. That's less than 1% of a 100-psec risetime. For any object of this tiny physical scale, a lumped-element model should suffice. Years ago, Terry Edwards reproduced in his book [38] (also see [39] ) a good lumped-element model for a right-angle bend. His model indicates that a right-angle bend has two primary effects: a slight delay plus some excess lumped capacitance. You might imagine that as a signal traverses a right-angle corner, the trace appears to grow wider at the corner. This simple idea explains why you see an excess capacitance (lower impedance) near the corner.

For an 8-mil wide, 50- W microstrip transmission line in FR-4, the excess lumped capacitance works out to 0.012 pF. Assuming that you are using 100-psec rise and fall times, the size of the reflected signal that bounces off this capacitive discontinuity is 0.30% (that's 0.003) of the incoming step amplitude. I conclude from this analysis that the reflection from a single corner is too small to worry about. (The reflected signal size scales in proportion to the trace width and inversely with rise and fall times.)

Some people worry that conduction electrons are traveling so fast that they won't be able to make it around a square corner. Perhaps they might reflect back or fly off into space. Such arguments are ridiculous. Sure, individual electrons move at high speeds, but their aggregate drift velocity is less than 2.5 cm/s (1 in./s) as they bounce from atom to atom. Your average electron smacks into something and changes directions billions of times in a length of 10 mils. Electrons don't have any trouble banging around a corner.

Might the electric-field concentration at a sharp, pointy corner create a lot of radiation? Hogwash. As a trace rounds a corner, it stays a constant distance from the underlying reference plane the whole way. The electric field intensity from trace to plane doesn't radically vary at any point along this track except for a modest perturbation in the vicinity of the actual pointy tip of the corner. It's true that a microscopic electric-field probe directly adjacent to the corner would detect this field concentration. However, measurements taken from farther away aggregate radiation from the whole trace, not just the corner. The corner, because it is so small, cannot noticeably affect the far-field radiation.

Layout professionals often point out that modern layout systems already round off all the outside corners, assuming that this rounding eliminates the square-corner effect. It doesn't. Rounding the corners removes 21% of the copper in the corner. Edwards shows that you must remove 70% to 90% of the copper from a right-angle bend to neutralize (to first order) the excess capacitance. Rounding removes only a small fraction of the required amount of copper. Rounded-corner right-angle bends work well in digital designs not because they are rounded, but because the corners are too tiny to cause significant problems in the first place.

Today, only microwave designers need to worry about right-angle bends. At microwave speeds, roughly 10 times the rate of most digital designs, parasitic capacitance presents 10 times more of a problem. Additionally, microwave designers often use big, fat, 100-mil traces to reduce skin-effect losses, so their corners appear electrically 10 times bigger. Lastly, they also tend to linearly cascade multiple stages. Cascading sums the imperfections in each stage, making microwave designs about 10 times more sensitive to tiny imperfections. Overall, contemporary microwave designs can be 1,000 times more sensitive to right-angle bends than are digital designs.

As digital designs push toward higher speeds, you may eventually reach a point where the right-angle bends begin to matter. For example, corners are just beginning to affect the design of 10-Gbps serial connections, and they also contribute perceptibly to skew in certain poorly routed differential pairs. If you accumulate oodles of corners, as in a serpentine delay structure, you may begin to see a little extra delay. Other than these extreme applications, right-angle bends remain electrically transparent.

Microwave designs are far more sensitive to right-angle bends than digital designs.

Some manufacturing engineers complain about the use of right-angle bends when using wave-soldering equipment. They worry that wayward solder balls or solder flux will get trapped in the inside corners. With reflow soldering and good soldermasking, neither should be a problem. I have heard no other credible negative comments about the manufacturability of right-angle bends, but I am always happy to hear from others whose experience may differ .

High Speed Digital Design Online Newsletter , Vol 2, Issue 25

Gary Griffin writes

I would like to know the effects of short pcb trace stubs and pcb vias, and how to eliminate or reduce them. The stubs could be short traces needed to hook a bus up to a socket, or something like that.

Vias are a necessary evil, but how can they be made more transparent to the high-speed signal? The speeds I am talking about range from 400MHz to 3GHz (digital and analog).

Reply

Thanks for your interest in High-Speed Digital Design .

Regarding socket stubs, there isn't much you can do except to not have them (i.e., don't use sockets). I know that's impractical in many cases.

About vias,

1. Blind or buried vias are smaller and have less effect than full-sized vias.
2. When your trace is adjacent to one power (or ground) plane, and then jumps through a signal via to run adjacent to a different power (or ground) plane, place a bypass capacitor in the vicinity to help returning signal currents follow along (any bypass connecting the reference planes helps returning signal currents jump from plane to plane), or
3. Better yet, route your trace so that it pops back and forth between two planes which carry the same DC potential. You can then use a plane-to-plane via near the signal via to help returning signal currents jump from plane to plane, or
4. Even better than that, route your trace so that it pops back and forth between the two sides of a single plane. In this case no special return current provision is necessary.
5. If your via can be modeled as a simple lumped-element capacitive discontinuity, consider addressing it with the technique discussed in Section 5.3.1.3, "Potholes". If your via looks like an inductive discontinuity, the same mathematical approach applies, only you will want to make Z 1 less than Z (see 5.3.1.4, "Inductive Potholes").
6. The use of both-ends termination (series and source termination used together), often combined with differential signaling, will produce a circuit with a great deal of immunity to the reflections caused by vias. Simulate this one to see the difference. To make use of this idea, you will of course need a receiver with sufficient sensitivity to work with the half-sized signal that results from using both-ends termination.

   Good luck!

Article first published in EDN Magazine , August 17, 2000

I'm designing a 2.5-Gbps, OC-48 transceiver card. Between two chips on my board I have several discrete capacitors and resistors to slow the edges and pad the signal. It seems that the very short 2.5-cm (1-in.) trace that I'm using is covered more with part pads than with 50- W trace. My software calculates the [trace] impedance but does not consider these parts . What effect does the pad size have on my trace impedance, and can I neglect it?

Code Cubitt

The component pads have a big impact on trace impedance, and at 2.5 Gbps, you will really notice it. The basic effect is that each pad contributes a little extra parasitic capacitance C to the trace. A single 1206 pad contributes about 0.72 pF, estimated at 31 pF/cm 2 for a 0.0127-cm thickness of FR-4, (200 pF/in. 2 for a 0.005-in. thickness of FR-4), ignoring fringing fields at the edges.

If you space the pads equally along the line, and if the spacing is a small fraction of the signal rise and fall time, then the parasitic capacitance of the pads merely reduces the line impedance. A general rule for the line impedance Z is

Equation 5.23

Adding parasitic capacitance increases C . According to the formula, when you increase C , you decrease Z . By whatever ratio you increase the apparent capacitance of the trace, by the square root of that ratio you reduce the effective loaded impedance of the structure.

Capacitive loading decreases the effective trace impedance.

The exact amount of reduction in the apparent impedance of a loaded trace is proportional to the square root of the ratio of how much capacitance would have been distributed along a raw, unloaded transmission line of the same dimensions, divided by how much capacitance you end up with after you add the equally spaced loads.

A good formula for the total capacitance C LINE , distributed along an unloaded transmission line, is

Equation 5.24

If the total load capacitance added to the trace is C LOAD , you can write the impedance-reduction-ratio formula as

Equation 5.25

If the loads are equally spaced, at least you still have a transmission line with a defined (albeit rather low) impedance. You might consider shrinking the line width to get the impedance back up to your target value of Z .

Example of heavily loaded transmission line

Assume a transmission line with nominally 1.2 pF/cm of shunt capacitance. Add to that a collection of loads at 0.72 pF each, with a spacing of one load per cm.

The loaded impedance in this example will be 79% of the target design value.

If the loads are not equally spaced or if their spacing is too great, the signal bounces back and forth between the various capacitive discontinuities in a disagreeable manner. The worst reflection coefficient G that you can get from an isolated capacitive discontinuity in the middle of an otherwise perfect transmission line is

Equation 5.26

If one section of your line has many loads, you should decrease the line width in that section to compensate but leave the line width at its normal size over the long unloaded sections.

Remember that loads sufficiently heavy to decrease the line impedance also increase the line delay. By whatever ratio the loads reduce the trace impedance, they increase the trace delay. The best way to reduce the effect of parasitic loading is to use smaller parts. The smaller the parts, the better (for example, 0603 is much better than 1206).

On a related subject, I've been told that the metallic film on most surface-mounted resistors is generally placed on only one face of the package. Such one-sided parts exhibit more parasitic capacitance to ground, and less inductance, when turned "face down" rather than "face up." If you want these parts to appear with a particular orientation on your reels, you have to ask for it.

Some engineers cut a little hole in the solid reference planes underneath the pads to reduce their parasitic capacitance. I am unaware of any inexpensive software or tools to help you determine the amount of cutting required, but I know microwave folks who use this trick all the time. They just try it and then adjust the hole size until it seems to work.

Full-fledged, 3-D electromagnetic-field-simulation packages can tell you what size hole to use. It seems a shame, though, to have to buy such a complicated software package and spend all that time learning to use it when you could just try a hole to see what happens. On the other hand, if you need to solve the reference-plane-hole problem many times in many situations, a good 3-D field solver could save you a lot of trial-and-error time.

Article first published in EDN Magazine , April 9, 1998

Let's say you can't fit your series termination in the ideal location, next to the driver. There isn't room. You have to place it a little further away than you'd like. Will it still work?

A series termination resistor is supposed to absorb high-frequency energy, damping reflections on the net. To perform at its best, it must be directly connected to a very low impedance source, presumably your driver. Anything placed in series with the termination resistor changes its value, making it less effective. That includes the short pcb trace, or connection stub, that hooks the driver to the termination resistor. Applications that need very accurate termination (like clock lines) should take this effect into account. Fortunately, we can easily calculate the degradation due to a connection stub. As long as the stub delay is less than 1/3 of the signal risetime, the approximations given below will be accurate to within 25%.

Place a series terminator no more than a small fraction of one risetime away from the driver.

The connection stub (Figure 5.17), because it connects at one end to a low-impedance driver, acts like a little inductor L STUB . This stub inductance acts in series with the termination resistor R 1 , adding to the impedance of the termination. If you add the impedance of the stub j w L STUB to the resistor value R 1 , you get a reasonable model for the combined termination impedance. To this termination impedance you must also add the natural output resistance and inductance of the driver. I'll assume you have set up the value of R 1 so that it, plus the natural output resistance of the driver, together match the line impedance Z , so the overall model of the termination impedance looks like this:

Equation 5.27

Figure 5.17. The returning echo from the far end encounters a composite load formed by the resistor R 1 , the inductance L STUB of the stub, plus the R S and L S of the driver.

The returning echo from the far end of the line, when it encounters termination network Z T , reflects a short pulse. This amplitude of the reflected pulse (as observed at the open -circuited far endpoint of the line) will be approximately

Equation 5.28

That's the theory, except for one embellishment the stub affects the risetime of the first incident waveform by a tiny amount. Keep the stub delay less than 1/3 of the risetime and you will hardly see this risetime degradation. (Thanks to Tom Giovannini and Joe Cahill for reminding me to mention this).

Example estimation of reflection from series terminator

Assume a BGA package with L S = 6000 pH, Trace impedances Z and Z STUB equal to 70 W , An ideal series-termination resistor located 72 ps from the driver, and A 3.3-v driver with a 1-ns risetime.

The series termination in this case, even though it is adjusted for an ideal value of resistance , fails to completely damp the reflections because of the associated package and stub inductance. As a result, you may need to wait for the ringing to decay in this example before sampling the signal.

Pay close attention to the length of your connection stub. Stub delays less than 1/3 of the signal risetime create residual reflections that can be approximated by [5.28]. Stub delays in excess of 1/3 of the signal risetime can create a significant resonance that grows rapidly with increasing trace length. Don't stretch your luck. If you want 20dB or more of reflected-wave attenuation, use a stub delay of no more than 1/6 the risetime, a very good low-inductance package, and an accurate carbon-composition or low-inductance metal film resistor.

High Speed Digital Design Online Newsletter , Vol 2, Issue 7

Bob Haller writes

I agree that series termination is a very effective way to eliminate SI problems on networks, and generating a simple expression to handle effectiveness based on placement is a great idea. Can you please address the stub length of parallel, terminated nets [for] both inline and downstream parallel termination?

When I am performing parallel termination, it is often difficult to sequence the termination in the proper order (driver, long line, load, short stub, and termination). I have found that if the stub length is kept very short, and edge rates are not excessively fast, terminating in the alternate sequence (driver, long line, termination, short stub, and receiver) can be as effective and save significant routing channels when surface-mounted components are utilized (especially high pin count BGAs).

Reply

Thanks for your interest in High-Speed Digital Design .

Great idea! When working with very fast edge rates, the sequencing of the end terminator and its associated load can make a measurable difference in signal quality. We can use "short stub" analysis to predict the effect. If you hook up a net in this sequence: driver, long line, terminator, short stub, and receiver, the additional short stub (which is open -circuited at both ends), will act as a small lumped-element capacitor (Figure 5.18).

Figure 5.18. A dangling stub adds to the total load capacitance at the end of the trace, increasing the size of the reflected pulse.

This small capacitance of the stub, along with the parasitic input capacitance of the receiver pin, creates an imperfection in the termination network. When the first incident wave arrives from the driver, part of that wave, a small pulse, bounces off the imperfection and returns to the driver.

The small reflected pulse travels backwards along the line to the driver, where it bounces again (off the low impedance of the driver output) and returns, one round-trip time later, to the receiver. What we observe at the receiver is an initial rising edge, followed one round-trip time later by a secondary pulse. If the initial reflected pulse is sufficiently small, all tertiary and subsequent events will be of negligible amplitude.

Assuming the delay of the short stub is less than 1/3 of a risetime, you can model the amplitude of the reflected pulse:

Equation 5.29

The relative accuracy of this formula is about +/- 25 percent.

A stub whose length equals 10% of the signal rise (or fall) time, and whose impedance equals the impedance of the main signal trace, contributes a reflection 5% the size of the incoming step. A stub of 1/3 the length of the signal rise (or fall) time reflects on the order of 20% of the incoming step, destroying the effectiveness of the termination.

A signal routed first to the receiver, then on to a parallel termination at the bitter end of the line, suffers no additional load capacitance other than the receiver itself (Figure 5.19).

Figure 5.19. A fly-by termination suffers the capacitance of the receiver, but no additional reflection from the termination.

High Speed Digital Design Online Newsletter , Vol 4, Issue 14

Bill Daskalakis writes

I am aware that the driver output impedance or source impedance of a device may vary depending on whether it is in a high or low state. I have found that the source impedance may be as high as 200 ohms for the logic-1 state and as low as 20 ohms for a logic-0 state. How are you supposed to calculate an appropriate series termination when you have such a large variance in source impedance?

Note: I assume you are supposed to calculate the series resistance from the equation R T = Z - R S ,

Reply

Thanks for your interest in High-Speed Digital Design . Not only is there a wide variation in impedance from the high state to the low state, but there is an even wider variation from chip to chip, and between manufacturers of the same chip, and over the allowed operating temperature range, and over the allowed power-supply voltage range.

The on-state output impedance of a partially turned-on FET is very difficult to control. It depends quadratically on the exact value of the gate-switching threshold, which varies wildly depending on everything else. Of course, you get huge variations in the output impedance.

If you had access to +/- 20V supply rails that you could use to overdrive the FET gates in your I/O circuit (as is commonly done in switching-power-supply circuits), each FET would then turn on completely, producing an output resistance dependent on nothing but the bulk resistivity of your silicon and the size of the FET. As it is, most digital designs underdrive the gates, barely turning on the transistors , leaving the circuit quite sensitive to changes in its environment.

You also are fighting the tendency of most chip designers to make the pull-up side of the totem-pole output circuit fundamentally weaker than the pull-down side. I'm not a chip design expert, but I believe this has something to do with the superior carrier mobility available within the N-channel FET on the bottom of the totem pole as compared to the P-channel FET on the top. A larger topside FET could ameliorate the problem, but only at the expense of significant additional output capacitance (which becomes a problem in the tri-state condition).

As you have noticed, it is impossible given the specifications you have quoted to construct a series-terminated transmission line with sufficiently good termination to ensure first-incident-wave switching with a full-amplitude output signal.

If you can afford to wait a few round-trip times, however, your gate performs admirably. Assuming you use transmission lines with a 65-ohm impedance, the gate output impedance will be mismatched by a ratio of no worse than 3.25:1 in either direction (either 200/65 or 65/20 equals about 3.2), producing a reflection coefficient no greater than 53%. After five round trips, the residual reflection will die down to less than 5%, at which point you can safely clock the line. That's the way you are supposed to use this gate. If you can't afford to wait, you need a more accurate series termination.

What you must do to construct an accurate series-terminated configuration is use a driver with a much smaller output impedance. For example, consider the case of a driver whose output impedance varies from 1 to 10 ohms. Even though 10:1 is a huge variation in percentage terms, it is a small variation in absolute terms compared to 50 ohms. I may therefore place 45 ohms in series with this driver to produce an output structure whose impedance varies from 46 to 55 ohms, a pretty darn good match to a 50-ohm transmission line.

Alternately, you could use a current-source output circuit having an output impedance much greater than 50 ohms and then place an accurate resistor in parallel with the output to control the source impedance.

Either way, you end up using a good resistor to provide your well-controlled output impedance.

In the bipolar world you have other options available. For example, an emitter-follower output circuit biased with a small but constant output current exhibits a fairly well-controlled output impedance. ECL drivers (if properly biased) make use of this property to synthesize an output impedance very close to 10 ohms.

Article first published in EDN Magazine , December 21, 2000

Suppose you are connecting a 75- W cable to a piece of 50- W test equipment, or perhaps you are hooking up a pc-board trace to an unusual cable. If the transmission lines on either side of the connecting junction are long (compared with the signal rise or fall time) and if the shift in impedance is significant, reflections from the junction may degrade your signal. To fix the degradation problem, you can add circuitry at the junction.

The objectives for junction-matching circuitry vary according to your needs. Sometimes you want to cleanly pass signals in just one direction, the other direction, or both. Whatever the direction of signal flow, you want the signals to traverse the junction with minimal distortion, attenuation, and reflections. You can configure the circuit in Figure 5.20, called a resistive matching pad, to accomplish all of these objectives. The same basic circuit works for either single-ended or differential configurations.

Figure 5.20. A resistive pad matches two circuits with characteristic impedances Z 1 and Z 2 .

In AC- coupled applications, in which no meaningful DC content exists, you can use a transformer to modify the circuit impedance. Examples of wideband applications with no meaningful DC content include audio, video, and some data signals specially coded to enforce an equal number of ones and zeros (such as Manchester data coding or 8B10B coding). The transformer is a good component to use for impedance translation, because by winding different numbers of turns on the primary and secondary of the core , you can amplify (or attenuate) the voltage at the expense of an opposite change in current. Unfortunately, transformers don't work at DC.

In narrowband applications, such as carrier-based AM or FM radio, you can sometimes use resonant-circuit tricks to accomplish impedance transformation. A classic example is the resonant pi filter. It can accomplish voltage amplification (or attenuation) over a narrow band of frequencies but not over a wide band .

Random digital data, whose spectrum spreads across a vast range from DC to daylight , renders useless all standard narrowband and AC-coupling tricks. The only passive circuits that guarantee good impedance translation for wideband signals are resistive pads.

The only passive circuits that guarantee good impedance translation for wideband signals are resistive pads.

You can configure the matching pad shown in Figure 5.20 for left-to-right transmission, right-to-left transmission, or both. Table 5.6 presents the required component values and lists the performance for each application.

Each row of Table 5.6 shows values for R 1 and R 2 . The signal gain G (never bigger than unity) and reflection coefficient G (bounded by 1) are then given for signals traveling in either direction. Without loss of generality, the table assumes that Z 1 < Z 2 . (If your circuit is the other way around, then look at Figure 5.20 in a mirror.)

Table 5.6. Matching Pad Performance

When you configure the circuit for optimal operation in one direction, the reflection coefficient in the opposite direction is not very good. In fact, it's worse than with a raw, unmatched junction. Sometimes such lopsided performance is acceptable. For example, with a good source-terminated network (source on the left), when the driver emits a fresh edge, you don't really care what bounces off the junction. The first bounce merely returns to the source termination and dies. You do, however, care about the signals that reach the end and then bounce off the massive open-circuited endpoint. These signals, on their return trip, take a second pass across the junction, and the reflection coefficient from right to left mostly determines the performance of the system in this circumstance. For a source-terminated application with Z 1 < Z 2 , choose the optimal right-to-left pad. For an end-terminated driver on the same line, the optimal left-to-right pad works best. The both-ends termination (using both source and end-termination) is the least sensitive of all configurations to reflections at the junction. With both ends terminated, your circuit may not need a matching network at all.

To match two differential circuits with differential impedances Z 1 and Z 2 respectively, place R 1 directly between the two conductors of impedance Z 1 . Then split R 2 into two resistors, each of value R 2 /2, and put one in series with each conductor of impedance Z 2 .

Article first published in Electronic Design Magazine , August, 1997

Crosstalk is a fact of life in modern digital systems. We can't eliminate it, but it's our job to figure out how to control it, manage it, and just plain live with it.

Consider the circuit in Figure 5.22. In the terminology of crosstalk, the gate at position A is the aggressor, and the gates at positions D and F are the victims. Gates C and E remain stuck at zero for the duration of this discussion.

Figure 5.22. Crosstalk for short, heavily-loaded lines is highly directional.

Whenever aggressor A changes state, we observe a characteristic crosstalk waveform at both victims. Those of you doing dense, high-speed designs probably recognize this all-too-familiar scenario.

One of the fascinating things about crosstalk is its directionality. Crosstalk waveforms are a function of the orientation of the driver and receiver. For example, in Figure 5.22 the two victim circuits have opposite orientations. In response to a rising edge on the aggressor, the waveforms at D and F display opposite polarities.

Crosstalk is directional.

The differing polarities suggest that we are not dealing with capacitive crosstalk. Many digital engineers assume that crosstalk is primarily a capacitive effect. It isn't. Mutual capacitance acting alone would cause the same polarity of crosstalk at both endpoints.

The differing polarities indicate that the interference is due (at least in part) to mutual inductive coupling. That's the same kind of coupling you get in a transformer. Everyone knows that reversing the leads on the primary winding of a transformer will reverse the polarity of the voltage on the secondary. Coupled pcb traces act in much the same way. If you think of each pcb trace as a little loop of current, you can see how the "crosstalk" transformer works.

First, imagine current from the gate at position A flowing out through the aggressor trace to the load at B . From there the current returns, along the power and ground system, back to the source at A . The aggressive current thereby makes a loop. Think of this loop as the primary winding of a transformer.

One secondary winding of that same transformer lies nearby. It is the loop formed starting with the gate at position C , moving out along the victim trace to the load, and back along the power and ground system, returning to the gate at C .

The primary and secondary loops acting together behave almost exactly like a weakly coupled, single-turn transformer.

Because the orientation of the bottom circuit E F opposes the top circuit C D , the mutual inductive crosstalk captured at endpoint F is exactly opposite that captured at D . This behavior corresponds to the action of a transformer having two secondaries wound in opposite directions. One receives a positive signal, the other, negative.

The existence of transformer-type mutual inductive coupling between traces has profound implications for digital designs. For one thing, it implies that crosstalk varies depending on the applied load.

For example, Figure 5.22 assumes a short pcb trace such that the driver and load behave as if directly coupled. In this case the aggressor current varies strongly as a function of the applied load. The heavier the load, the more aggressor current the circuit draws and the more crosstalk it generates. The triple-loaded network in the figure therefore generates more crosstalk than would a similar net, with a similar topology, having only one load.

In contrast, a simple mutual-capacitance coupling model incorrectly predicts a decrease in crosstalk as loads are added to the circuit due to the smaller d v /d t present in the aggressive circuit when heavily loaded.

The loading effect is particularly acute when driving banks of SIMM memory modules. Such traces tend to be very short, but heavily loaded. When you insert the second SIMM module, the drive current rises markedly, creating noticeably more crosstalk.

If you are trying to debug a crosstalk problem on a dense multilayer board, knowledge of how trace loading affects crosstalk can help you understand, and fix, crosstalk problems.

If you are trying to manage crosstalk from first principles so it comes out right on the first spin, look into the new crosstalk prediction tools that feature IBIS I/O modeling. Many of these new tools are capable of calculating crosstalk, including the loading effects, in an automated, highly efficient manner.