Article first published in EDN Magazine , August 3, 1998
An ideal digital clock, from the standpoint of system timing, is an infinite succession of very fast-edged, identical pulses with a perfectly repeating structure. Unfortunately, from an electromagnetic compatibility (EMC) perspective, such a clock is also the worst of all possible signals. It radiates like crazy. This situation is calmly referred to in polite engineering circles as a fundamental tradeoff . Late at night, when we engineers let our hair down, I've heard other terms used to describe it.
The problem with a simple, repetitive signal like a clock is that all its power can become concentrated at a relatively small number of discrete frequencies. When these discrete frequencies leak out of your product's packaging into the outside world, all the radiated clock power is concentrated in a small number of radiated modes.
Clock modulation of any kind complicates the attachment of your product to any form of truly synchronous logic.
Data signals don't do this. Random data signals spread their power among a much larger number of radiated modes, each with a smaller average power. That's better, because both FCC and EN emissions regulations are written to penalize the worst-case (peak) radiation in any given mode.
Although the data nets in your product undoubtedly radiate more total power than do the clocks, the data nets usually contribute less to the FCC/EN peak radiation measurements, because the radiation from the data nets is spread evenly at a relatively low level across the vast territory of the electromagnetic spectrum.
Over the years , various techniques have been proposed for modulating, or dithering, the clock frequency in order to break up the accumulated power into a larger number of new modes, each with a reduced power content. If the new modes are separated from each other by more than 100 KHz, which is the effective bandwidth used for FCC/EN spectral power density measurements, the peak power measured within each 100 KHz band will be reduced. Such proposals are backed by solid theoretical reasoning and, for the most part, they are technically sound. Modulating the clock really does reduce the peak measured radiation. Unfortunately, the practical realization of this technique comes at a very high cost. A proper appreciation of the architectural cost of a modulated clock may be gained by considering the many uses to which a clock may be put.
First and foremost, the clock directs the synchronous neural firings of your product's digital brain. When working with a purely digital product architecture, you might conclude that you need merely to guarantee a minimum clock period. Any modulation or dither above and beyond the minimum period should, theoretically, have no impact on the correctness of the computed results. Dither may perturb the timing of the final result (it will always be slower than if you had run the machine continuously at full speed), but it should not affect the correctness ”at least that's the theory.
The practical side of the matter is that intentional clock modulation of any kind complicates the attachment of your product to any form of truly synchronous logic. For example, a modulated clock can never be used as the reference clock input to any advanced data communication transceiver (Ethernet, Fibre Channel, FDDI, ATM, SONET, or ADSL). These parts require a pristine, jitter-free reference clock. When connected to a jittery clock, these transceivers may fail to lock or may lock poorly, leading to data errors or other flaky behavior. Never use an intentionally modulated clock as the reference input for any kind of data communication transceiver.
For similar reasons, you'll find a modulated clock unsuitable as a main system clock for any modern high-performance CPU. These parts all contain internal clock multiplier circuits (PLLs) which are very sensitive to jitter in the reference clock. The Semiconductor Industry Association roadmap [129] implies that more and more components will incorporate clock multipliers in future years. This is a trend you won't want to forgo.
Finally, in case you are not yet convinced, I'd like to point out that wireless communication is becoming progressively more important in many applications. Modulated clocks should not be used as a reference source for RF-communication systems. Especially for direct-sequence spread spectrum links, where the data rate and the communications modulation rate (the chip rate) are related in a fixed manner, it is important to have a stable, jitter-free system clock for the transfer of data to and from the RF subsystem.
In each of the three cases I've outlined here, it is of course still possible to connect a jittery clock domain to a purely synchronous subsystem. The connection requires a clean reference clock for the synchronous side of your product (in addition to the jittery modulated clock you already have), plus a dual-ported asynchronous FIFO to connect the jittery clock domain to the purely synchronous domain. Why bother with this sort of architecture?
In this author's opinion, if control of EMC is your objective, you will be better served by any combination of the following techniques:
- Use solid power and ground planes in your pcb.
- Minimize the trace-to-plane spacing.
- Use thin packages, keeping all signals close to the board.
- Slow down the rise/fall time of the clock driver.
- Use differential clock transmission.
- Use a lower-voltage clock driver (like LVDS or GTL).
Any of these techniques will deliver the clock you need at a cost you can afford.
Postscript September 3, 2002 ”Some CPU manufacturers now make PLL-based clock multipliers that tolerate specific amounts of intentional clock modulation, but I still think it's a bad idea.
|