Reduced-Voltage Signaling

A number of clock repeater chips use reduced-voltage-signaling. By reduced-voltage signaling I refer to the use of a peak-to-peak voltage swing intentionally made smaller than the V CC voltage supplied to the chips. Examples of reduced-voltage logic systems include BTL, GTL, ECL, SSTL, and LVDS logic.

One advantage of reduced-voltage clock signaling is a tremendous savings in overall system power. Another big advantage is lowered EMI due to the smaller swing.

The price you must pay for the use of reduced-voltage components is an increased susceptibility to noise. Noise may come in the form of crosstalk from the other regular-voltage logic chips on the same system. Extra spacing must be enforced between any low-voltage pcb traces and traces used by other logic families. Noise may also come in the form of environmental radiation from nearby RF sources, ESD, or EMP events.

POINT TO REMEMBER

• Reduced-voltage clock signaling saves power and cuts EMI at the expense of noise susceptibility.